Semiconductor integrated circuit

Abstract

The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.

1 - 10 . (canceled) 
   
   
       11 . A semiconductor integrated circuit comprising:
 an external terminal;   external input/output buffer means;   power supply detecting means;   power on reset means; and   a first circuit area having a plurality of internal circuits,   wherein the power supply detecting means outputs a power supply voltage detection signal indicating that an externally supplied power supply level has reached a predetermined state,   wherein the power on reset means receives the power supply voltage detection signal, instructs an initial setting operation of at least one said internal circuit at a predetermined timing and, in response to completion of the initial setting operation on the at least one internal circuit, sets a predetermined initial state of any of a high-level output, a low-level output, and a high impedance of the external input/output buffer means to a state where an input/output operation can be performed,   wherein the power on reset means outputs a signal for ensuring an initial state of a predetermined circuit node until the initial setting operation is instructed to the at least one internal circuit,   wherein a first power supply level is supplied to the external input/output buffer means, the power supply detecting means, and the power on reset means, and a second power supply level is supplied to the at least one internal circuit, and   wherein the power supply detecting means has a first circuit for detecting supply of the first power supply level and a second circuit for detecting supply of the second power supply level and sets, as the power supply voltage detection signal, an AND signal between a detection result of the first power supply level by the first circuit and a detection result of the second power supply level by the second circuit.   
   
   
       12 . The semiconductor integrated circuit according to  claim 11 ,
 wherein when the power supply detecting means detects, after detection of supply of the first power supply level and the second power supply level, cessation of the supply of the second power supply level by the second circuit, the external input/output buffer means is changed from the operable state to a predetermined state of any of a high-level output, a low-level output, and a high impedance.   
   
   
       13 . The semiconductor integrated circuit according to  claim 12 , further comprising:
 a second circuit area including system control means, and   wherein the system control means receives an instruction of initial setting operation of the at least one internal circuit, receives an external clock signal, controls the initial setting operation of the at least one internal circuit synchronously with the received clock signal and, on completion of the initial setting operation, sends an initialization completion signal to the power on reset means.   
   
   
       14 . The semiconductor integrated circuit according to  claim 13 ,
 wherein supply of the second power supply level to the first circuit area can be selectively stopped in a state where the second power supply level is supplied to the power supply terminal,   wherein supply of the second power supply level to the second circuit area is always supplied, and   wherein the system control means is formed in the second circuit area.   
   
   
       15 . The semiconductor integrated circuit according to  claim 14 ,
 wherein an internal power supply switch controller for controlling whether the second power supply level is supplied to the first circuit area or not is provided in the second circuit area,   wherein the system control means initially sets the internal power supply switch controller to supply the second power supply level to the first circuit area in response to an instruction of the initial setting operation from the power on reset means,   wherein the at least one internal circuit includes a central processing unit and a peripheral circuit, and   wherein the system control means initializes an internal state of the central processing unit and sets a predetermined register of the peripheral circuit to an initial value in response to an instruction of the initial setting operation from the power on reset means.