Flash Memory Devices and Methods of Fabricating the Same

Abstract

Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed method further comprises forming an etching groove in the active region. The etching groove separates a source region and a drain region. The disclosed method also comprises growing an epitaxial layer within the etching groove; forming a gate insulating layer on the epitaxial layer; depositing a first polysilicon layer on inner sidewalls of the opening and on the gate insulating layer; forming a dielectric layer on the first polysilicon layer; and depositing a second polysilicon layer on the dielectric layer.

1 . A flash memory device comprising:
 a substrate having a groove formed within a channel area;   a source region formed in the substrate on a first side of the groove;   a drain region formed in the substrate on a second side of the groove;   a channel layer formed within the groove;   a dielectric layer formed over the source and drain regions, the dielectric layer defining an opening;   a gate insulating layer formed in the opening and on the channel layer;   a floating gate formed on the gate insulator layer and on inner sidewalls of the opening; and   a dielectric layer formed on the floating gate; and a control gate formed on the dielectric layer.   
   
   
       2 . A flash memory device as defined by  claim 1 , wherein the channel layer is an epitaxial layer. 
   
   
       3 . A flash memory device as defined by  claim 1 , further comprising a silicide layer formed on the control gate, wherein the silicide layer has a planarized top surface. 
   
   
       4 . A flash memory device as defined by  claim 1 , wherein the dielectric layer defines a generally vertical opening, and the control gate substantially fills the generally vertical opening. 
   
   
       5 . A flash memory device comprising:
 a substrate:   an etching mask layer defining an opening;   a floating gate on a bottom and inner sidewalls of the opening, the floating gate defining a floating gate opening; a dielectric layer on the floating gate, the dielectric layer defining a dielectric layer opening at least partially extending into the floating gate opening; and   a control gate on the dielectric layer, the control gate substantially filing the dielectric layer opening and having a generally T-shaped cross-section.   
   
   
       6 . A method as defined in  claim 5 , wherein the floating gate extends above the etching mask layer. 
   
   
       7 . A method as defined in  claim 5 , further comprising:
 an etching groove in an active region of the substrate separating a source region and a drain region; and   a channel layer within the etching groove.