Chip package and method of fabricating the same

Abstract

A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.

1 . A method of fabricating a chip package, comprising:
 providing a thin metal plate having an upper surface and a lower surface, wherein the upper surface of the thin metal plate has a first protrusion part, a second protrusion part and a plurality of third protrusion parts, the second protrusion part is located between the first protrusion part and the third protrusion parts, and the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another;   providing a chip having an active surface, a back surface and a plurality of chip bonding pads, wherein the chip bonding pads are disposed on the active surface;   fixing the back surface of the chip on the first protrusion part;   forming a plurality of first bonding wires and a plurality of second bonding wires, wherein the first bonding wires electrically connect the chip bonding pads to the second protrusion part respectively, and the second bonding wires electrically connect the second protrusion part to the third protrusion parts respectively;   forming an upper encapsulant and a lower encapsulant, wherein the upper encapsulant encapsulates the upper surface of the thin metal plate, the chip, the first bonding wires and the second bonding wires, the lower encapsulant encapsulates the lower surface of the thin metal plate, and exposes locations where the first protrusion part, the second protrusion part and the third protrusion part are connected to one another; and   etching the thin metal plate by using the lower encapsulant as an etching mask until the first protrusion part, the second protrusion part and the third protrusion parts are electrically insulated from one another, so that the first protrusion part forms a die pad, the second protrusion part forms a bus bar, and the third protrusion parts form a plurality of leads.   
     
     
         2 . The method according to  claim 1 , wherein the thin metal plate comprises a copper foil. 
     
     
         3 . The method according to  claim 1 , wherein the first bonding wires and the second bonding wires are formed by a wire-bonding technique. 
     
     
         4 . The method according to  claim 1 , wherein the lower encapsulant comprises a plurality of recesses exposing locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. 
     
     
         5 . The method according to  claim 4 , further comprising forming a plurality of encapsulant inside the recesses of the lower encapsulant. 
     
     
         6 . A chip package, comprising:
 a chip having an active surface, a back surface and a plurality of chip bonding pads, wherein the chip bonding pads are disposed on the active surface;   a lead frame having an upper surface and a corresponding lower surface, the lead frame comprising:
 a die pad having the back surface of the chip fixed thereon; 
 a plurality of leads surrounding the die pad; and 
 at least one bus bar located between the die pad and the leads; 
   a plurality of first bonding wires electrically connecting the chip bonding pads to the bus bar respectively;   a plurality of second bonding wires electrically connecting the bus bar to the leads respectively;   an upper encapsulant encapsulating the upper surface of the lead frame, the chip, the first bonding wires and the second bonding wires; and   a first lower encapsulant encapsulating the lower surface of the lead frame, wherein the first lower encapsulant has a plurality of recesses exposing the upper encapsulant between the die pad and the bus bar, the upper encapsulant between the bus bar and the leads and the upper encapsulant between two adjacent leads.   
     
     
         7 . The chip package according to  claim 6 , further comprising a plurality of second lower encapsulant formed inside the recesses of the first lower encapsulant.