Column sample-and-hold cell for CMOS APS sensor

Abstract

A sample and hold readout circuit, and method of operation which minimizes fixed pattern noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output. This is accomplished by eliminating the crowbar between the storage elements in the sample and hold circuit. Switches are added to isolate the sample and hold circuit from the column line coupled to the pixel array and to short the front plates of the capacitors together. Activating these switches allows the signals stored in the sample and hold circuit to be transferred downstream without the use of a crowbar switch.

1 . A sample and hold circuit for an imager, comprising:
 a selection circuit for selectively coupling a common node to a pixel output column line and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals, said selection circuit for selectively uncoupling said common node from said pixel output column line and for selectively coupling said first and second storage elements through said common node to transfer said stored respective pixel output signals to an output stage.   
     
     
         2 . The sample and hold circuit of  claim 1 , wherein said selection circuit further comprises:
 a first switch, disposed between said common node and said column line.   
     
     
         3 . The sample and hold circuit of  claim 2 , wherein said selection circuit further comprises:
 a second switch, disposed between said common node and said first storage element; and   a third switch, disposed between said common node and said second storage element.   
     
     
         4 . The sample and hold circuit of  claim 3 , wherein said selection circuit selectively couples said common node to a first voltage. 
     
     
         5 . The sample and hold circuit of  claim 4 , wherein said first voltage is a load voltage. 
     
     
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         8 . A sample and hold circuit for an imager, comprising:
 a first switch for selectively coupling a common node to an imager array column line;   a first storage circuit for sampling and holding a first signal from said imager array column line, said first storage circuit having an input side and an output side;   a second switch for selectively coupling the input side of said first storage circuit to said common node;   a second storage circuit for sampling and holding a second signal from said imager array column line, said second storage circuit having an input side and an output side; and   a third switch for selectively coupling the input side of said second storage circuit to said common node.   
     
     
         9 . The sample and hold circuit of  claim 8 , further comprising:
 a fourth switch for selectively coupling the output side of said first storage circuit to an output stage; and   a fifth switch for selectively coupling the output side of said second storage circuit to said output stage.   
     
     
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         14 . A sample and hold circuit for an imager, comprising:
 a selection circuit for selectively coupling a common node to an imager column line and for sequentially coupling a first and second storage element to said common node to sample and store respective imager output signals, wherein said selection circuit further comprises:   a first switch, disposed between said common node and said imager column line;   a second switch, disposed between said common node and said first storage element;   a third switch, disposed between said common node and said second storage element; and   a fourth switch for coupling said common node to a load voltage.   
     
     
         15 . The circuit of  claim 14 , wherein said first and fourth switches being selected. 
     
     
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         18 . A sample and hold circuit for an imager, comprising:
 a selection circuit for selectively coupling a common node to an imager column line and for sequentially coupling a first and second storage element to said common node to sample and store respective imager output signals, wherein said selection circuit further comprises:   a first switch, disposed between said common node and said imager column line;   a second switch, disposed between said common node and said first storage element;   a third switch, disposed between said common node and said second storage element;   a fourth switch for coupling said common node to a load voltage; and   wherein said second and third switches being sequentially selected when said first switch being selected, said second and third switches being substantially contemporaneously selected when said first switch not being selected.   
     
     
         19 . A sample and hold circuit for an imager, comprising:
 a selection circuit for selectively coupling a common node to an imager column line and for sequentially coupling a first and second storage element to said common node to sample and store respective imager output signals, wherein said selection circuit further comprises:   a first switch, disposed between said common node and said imager;   a second switch, disposed between said common node and said first storage element;   a third switch, disposed between said common node and said second storage element; and   a fourth switch for coupling said common node to a load voltage.   
     
     
         20 . The circuit of  claim 19 , wherein said first and fourth switches being selected. 
     
     
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         35 . A semiconductor imaging device, comprising:
 a pixel array imager comprising:   a sample and hold circuit, comprising:   a selection circuit for selectively coupling a common node to a pixel output and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals.   
     
     
         36 . The semiconductor imaging device of  claim 35 , wherein said selection circuit further comprises:
 a switch, disposed between said common node and said pixel.   
     
     
         37 . The semiconductor imaging device of  claim 36 , wherein said selection circuit further comprises:
 a second switch, disposed between said common node and said first storage element; and   a third switch, disposed between said common node and said second storage element.   
     
     
         38 . The semiconductor imaging device of  claim 37 , wherein said selection circuit selectively couples said common node to a first voltage. 
     
     
         39 . The semiconductor imaging device of  claim 38 , wherein said first voltage is a load voltage. 
     
     
         40 . A processor system, comprising:
 a central processing unit;   array imager coupled to said central processing unit, said imager comprising:   a sample and hold circuit, comprising:   a selection circuit for selectively coupling a common node to a pixel output column line and for sequentially coupling a first and second storage element to said common node to sample and store respective pixel output signals, said selection circuit for selectively uncoupling said common node from said pixel output column line and for selectively coupling said first and second storage elements through said common node to transfer said stored respective pixel output signals to an output stage.   
     
     
         41 . The processor of  claim 40 , wherein said selection circuit further comprises:
 a first switch, disposed between said common node and said column line.   
     
     
         42 . The processor of  claim 41 , wherein said selection circuit further comprises:
 a second switch, disposed between said common node and said first storage element; and   a third switch, disposed between said common node and said second storage element.   
     
     
         43 . The processor of  claim 42 , wherein said selection circuit selectively couples said common node to a first voltage. 
     
     
         44 . The processor of  claim 43 , wherein said first voltage is a load voltage. 
     
     
         45 . (canceled) 
     
     
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         47 . A sample and hold circuit for an imager, comprising:
 a switching circuit for selectively coupling a sample and hold circuit to a pixel output column line and for sequentially coupling first and second storage elements to said pixel output column line through a first and second switch, respectively, to sample and store respective pixel output signals, said switching circuit for selectively uncoupling said sample and hold circuit from said pixel output column line.   
     
     
         48 . The sample and hold circuit of  claim 47 , wherein said switching circuit further comprises a third switch, disposed between said first and second switches and said pixel output column line. 
     
     
         49 . The sample and hold circuit of  claim 48 , further comprising:
 a fourth switch for selectively coupling a first voltage to said first and second storage elements through said second and third switches, respectively.   
     
     
         50 . The sample and hold circuit of  claim 49 , wherein said first voltage is a load voltage. 
     
     
         51 . A method of operating a sample and hold circuit in an imaging pixel array, said method comprising:
 selectively connecting a selected imager array column line to said sample and hold circuit;   selectively coupling said first storage circuit to said selected column line;   storing a first signal from said selected column line in said first storage circuit;   selectively coupling said second storage circuit to said selected column line; and   storing a second signal from said selected column line in said second storage circuit.   
     
     
         52 . The method of  claim 51 , further comprising:
 selectively disconnecting said selected column line from said first storage circuit, after said first signal is stored; and   selectively disconnecting said selected column line from said second storage circuit, after said second signal is stored.   
     
     
         53 . The method of  claim 52 , further comprising:
 selectively disconnecting said sample and hold circuit from said selected column line, after said first and second signals are stored.   
     
     
         54 . The method of  claim 53 , further comprising:
 selectively contemporaneously coupling input sides of said first and the input side of said second storage circuits while selectively coupling output sides of said first and second storage circuits to an output stage.   
     
     
         55 . The method of  claim 54 , wherein the selective coupling of the said first and second storage circuits to said output stage is controlled by a common signal. 
     
     
         56 . The method of  claim 55 , further comprising the step of initially coupling a clamp voltage to said first and second storage circuits. 
     
     
         57 . The method of  claim 56 , further comprising the step of coupling a load voltage to said first and second storage circuits prior to said storing of said first and said second signals.