Flexible on chip testing circuit for i/o's characterization

Abstract

The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.

1 . A flexible on-chip testing circuit for I/Os characterization of a plurality of I/O structures, said I/O structures comprising one of a multi-voltage IUT, and a single voltage IUT, said testing circuit utilizing a plurality of operational modes for measuring said I/Os characterization, said testing circuit comprising:
 a Standard Test Interface providing a functional testing of the plurality of I/O structures and for interfacing a STIOBISC with an external world;   a register bank module coupled to said standard test interface for storing a plurality of instructions, and for measuring a plurality of results;   a central processing controller (CPC) connected to said register bank module for fetching and executing the plurality of instructions, said controller comprising:
 a plurality of secondary state machines for measuring said I/Os characterization; and 
 a primary state machine interacting with the plurality of secondary state machines for interpreting the plurality of instructions; 
   one or more characterization modules controlled by said central processing controller and said register bank for measuring one or more parameters.   
   
   
       2 . The flexible on-chip testing circuit of  claim 1 , wherein said Standard Test Interface comprises an IEEE1149.1 logic. 
   
   
       3 . The flexible on-chip testing circuit of  claim 1 , wherein the one or more parameters are selected from a group comprising a propagation delay, and a voltage slew rate. 
   
   
       4 . The flexible on-chip testing circuit of  claim 1  further comprising an analog I/O port for applying an analog voltage. 
   
   
       5 . The flexible on-chip testing circuit of  claim 1  further comprising a test access port (TAP) for receiving and transmitting the plurality of instructions. 
   
   
       6 . The flexible on-chip testing circuit of  claim 5 , wherein said test access port comprises one of a tap data input port (TDI), and a tap data output port (TDO). 
   
   
       7 . The flexible on-chip testing circuit of  claim 1 , wherein the one or more characterization modules comprises a character slew module for measuring a voltage rise time, and a voltage fall time of a multi-voltage IUT. 
   
   
       8 . The flexible on-chip testing circuit of  claim 7 , wherein said character slew module comprising:
 a stepped delay generator (SDG) receiving an input clock to generate an inverted version signal (IUTVin), and a programmable time delayed version signal (PROBE_L), said generator being controlled by said central processing controller;   a voltage comparator comparing a reference voltage, and an output inversion voltage (IUTVout) to generate an output voltage;   a low to high voltage level shifter for scaling said time delayed signal (PROBE_L) to a pad voltage (PROBE);   a high to low voltage level shifter for scaling the output voltage signal to a core voltage signal;   an inverter and a multiplexer providing a toggle from a logic ‘0’ to logic ‘1’ to said output voltage, when said output inversion voltage (IUTVout) crosses said reference voltage; and   a flip flop circuit utilizing an inverted time delayed clock signal for sampling an output signal from said multiplexer.   
   
   
       9 . The flexible on-chip testing circuit of  claim 1 , wherein the one or more characterization modules comprises a delay characterization module for measuring a propagation delay of a multi-voltage input I/O cell. 
   
   
       10 . The flexible on-chip testing circuit of  claim 9 , wherein said delay characterization module comprising:
 an IUT terminal for receiving input signals from a pad;   an analog cell connected to said IUT terminal for transmitting said signals to a core, said cell providing an EDS protection;   a clipping circuit receiving an output from said analog cell for reducing a pad voltage level to a core voltage level, said clipping circuit utilizing a reference voltage (Vref);   a pulse generator circuit receiving an output from said clipping circuit for generating a pulse signal corresponding to an IUT delay; and   a time to delay converter receiving said pulse signal to convert from a pulse width time to a binary value.   
   
   
       11 . The flexible on-chip testing circuit of  claim 10 , wherein said analog cell comprises a small finite series resistance to provide a latch-up protection for a CMOS cell. 
   
   
       12 . A method of I/Os characterization testing for a plurality of I/O structures through a flexible on chip testing circuit comprising:
 loading a plurality of instructions into a register bank through a standard test interface port;   fetching and executing the plurality of instructions through a central processing controller (CPC), said instructions being stored in said register bank;   controlling a stimuli application to a plurality of IUTs through the central processing controller;   storing a plurality of results through one or more characterization modules;   shifting out the plurality of results through the standard test interface port; and   processing the plurality of results through a custom tool to obtain characterization results.