Fabrication method of semiconductor integrated circuit device
Abstract
In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.
Claims
exact text as granted — not AI-modified1 . A method of fabricating a semiconductor integrated circuit device, comprising the steps of:
(a) printing solder over a substrate; (b) inspecting said solder printed over said substrate; and (c) mounting circuit parts over said solder printed over said substrate, wherein the step(b) includes a three dimensions-inspecting and a two dimensions-inspecting, and wherein said three dimensions-inspecting and said two dimensions-inspecting are performed by using a common camera which is capable of switching between light sources and can illuminate a different light between said three dimensions-inspecting and said two dimensions-inspecting, thereby to evaluate said solder by using photographic images taken by said common camera.
2 . A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein said two dimensions-inspecting is performed after said three dimensions-inspecting.
3 . A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein said common camera is a CMOS area camera.
4 . A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein said light sources are LED illumination lamps.Join the waitlist — get patent alerts
Track US2008232676A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.