Semiconductor device and method for fabricating the same

Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

1 .- 17 . (canceled) 
     
     
         18 . A method of fabricating a semiconductor device including a trench-gate MISFET, comprising the steps of:
 (a) providing a semiconductor body having a first semiconductor layer thereon;   (b) forming a gate trench on a main surface of the first semiconductor layer;   (c) forming a gate insulating film on an inner wall of the gate trench;   (d) forming a gate electrode on the gate insulating film;   (e) forming a base region in the first semiconductor layer;   (f) forming a source region on the base region;   (g) forming an interlayer insulating film over the source region;   (h) after the step (g), forming a contact hole in the interlayer insulating film and first semiconductor layer to expose a side surface of the source region, said contact hole being extended to the base region;   (i) after the step (h), etching side walls of the interlayer insulating film to enlarge the contact hole and expose an upper surface of the source region; and   (j) after the step (i), forming a source wiring in the contact hole and over the interlayer insulating film,   wherein the source wiring is contacted with the side and upper surfaces of the source region.