Semiconductor integrated circuit device and method of producing the same

Abstract

A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

1 .- 7 . (canceled) 
   
   
       8 . A semiconductor integrated circuit device comprising a plurality of logic cells composed of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, m being a natural number, wherein:
 horizontal wiring connection within each logic cell and between the logic cells is constituted only in n upper wiring layers among the m wiring layers, n being a natural number with n<m; and   lower (m-n) wiring layers comprise first contact VIAs and first wiring patterns connected to respective first contact VIAs.   
   
   
       9 . The semiconductor integrated circuit device according to  claim 8 , further comprising at least one power supply cell comprising the CMOS-type base cell arranged on the semiconductor substrate and the m, n and (m-n) wiring layers, wherein:
 the lower (m-n) wiring layers of the at least one power supply cell comprise third contact VIAs disposed at positions corresponding to at least one grid of a power supply in the base cells and third wiring patterns connected to the third contact VIAs;   third wiring patterns of neighboring power supply cells are connected to each other; and   the at least one power supply cell is positioned adjacent to at least one of the logic cells.   
   
   
       10 . The semiconductor integrated circuit device according to  claim 8 , further comprising at least one GND cell comprising the CMOS-type base cell arranged on the semiconductor substrate and the m, n and (m-n) wiring layers, wherein:
 the lower (m-n) wiring layers of the at least one GND cell comprise fourth contact VIAs disposed at positions corresponding to at least one grid of a GND in the base cell and fourth wiring patterns connected to the fourth contact VIAs;   fourth wiring patterns of neighboring GND cells are connected to each; and   
     the at least one GND cell is positioned adjacent to the at least one logic cells. 
   
   
       11 . A semiconductor integrated circuit device comprising a plurality of logic cells composed of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, m being a natural number, wherein:
 horizontal wiring connection within each logic cell and between the logic cells is constituted only in n upper wiring layers among the m wiring layers, n being a natural number with n<m; and   lower (m-n) wiring layers comprise connection cells comprising second contact VIAs and second wiring patterns disposed immediately above respective second contact VIAs and connected thereto, the second contact VIAs connecting all connection points to the upper n layers, the connection points including at least a gate, a source, a drain and substrate potential.   
   
   
       12 . The semiconductor integrated circuit device according to  claim 11 , further comprising at least one power supply cell comprising the CMOS-type base cell arranged on the semiconductor substrate and the m, n and (m-n) wiring layers, wherein:
 the lower (m-n) wiring layers of the at least one power supply cell comprise third contact VIAs disposed at positions corresponding to at least one grid of a power supply in the base cell and third wiring patterns connected to the third contact VIAs;   third wiring patterns of neighboring power supply cells are connected to each other; and   the at least one power supply cell is positioned adjacent to at least one of the logic cells.   
   
   
       13 . The semiconductor integrated circuit device according to  claim 11 , further comprising at least one GND cell comprising the CMOS-type base cell arranged on the semiconductor substrate and the m, n and (m-n) wiring layers, wherein:
 the lower (m-n) wiring layers of the at least one GND cell comprise fourth contact VIAs disposed at positions corresponding to at least one grid of an GND in the base cells and fourth wiring patterns connected to the fourth contact VIAs;   fourth wiring patterns of neighboring GND cells are connected to each other; and   the at least one GND cell is positioned adjacent to the at least one logic cells.