US2008237682A1PendingUtilityA1

Semiconductor memory with conductive carbon

Assignee: CHIANG KUO-CHINGPriority: Mar 26, 2007Filed: Mar 25, 2008Published: Oct 2, 2008
Est. expiryMar 26, 2027(~0.7 yrs left)· nominal 20-yr term from priority
H10D 30/6741H10D 64/037H10D 64/035H10D 62/235H10D 62/121H10D 62/118H10D 30/691H10D 30/0413H10D 30/0411H10D 30/69H10D 30/681B82Y 10/00H10B 43/30H10B 41/30
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Claims

Abstract

A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation layer formed between the first and second gates; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.

Claims

exact text as granted — not AI-modified
1 . A non-volatile memory capable of storing binary information on a semiconductor substrate comprising:
 a dual gate structure formed over said semiconductor substrate, wherein said dual gate structure including a gate dielectric layer formed over said semiconductor substrate, and first and second gates formed over said gate dielectric layer, an isolation layer formed between said first and second gates;   a conductive carbon material with nano-scale formed under said gate dielectric layer; and   a doped regions formed adjacent to said conductive carbon material.   
     
     
         2 . The memory of  claim 1 , wherein said dual gate structure is a stacked configuration. 
     
     
         3 . The memory of  claim 1 , wherein said dual gate structure is a split gate configuration. 
     
     
         4 . The memory of  claim 3 , wherein a field oxide structure formed between said dual gate structure. 
     
     
         5 . The memory of  claim 1 , wherein said gate dielectric layer is high dielectric constant material. 
     
     
         6 . The memory of  claim 5 , wherein said gate dielectric layer includes (SiO 2 ), (HfO 2 ), (ZrO 2 ), (TiO 2 ), (HfTiO), (HfAIO), (La 2 O 3 ) or (LaAIO). 
     
     
         7 . The memory of  claim 1 , wherein said conductive carbon includes nano carbon tube. 
     
     
         8 . The memory of  claim 1 , further comprising silicide material formed over said doped regions. 
     
     
         9 . The memory of  claim 8 , wherein said silicide material includes TiSi 2 , CoSi 2  or NiSi. 
     
     
         10 . A non-volatile memory capable of storing binary information on a semiconductor substrate comprising:
 a dual gate structure formed over said semiconductor substrate, wherein said dual gate structure including a gate dielectric layer formed over said semiconductor substrate, and first and second gates formed over said gate dielectric layer, an isolation L-shape structure formed between said first and second gates, wherein a vertical portion of said L-shape structure attached on sidewall of said first gate, and a lateral portion where tunneling will be occurred is formed over said substrate; spacers formed on said L-shape structure to act as a second gate;   a conductive carbon material with nano-scale formed under said gate dielectric layer; and   a doped regions formed adjacent to said conductive carbon material.   
     
     
         11 . The memory of  claim 10 , wherein said gate dielectric layer is high dielectric constant material. 
     
     
         12 . The memory of  claim 11 , wherein said gate dielectric layer includes (SiO 2 ), (HfO 2 ), (ZrO 2 ), (TiO 2 ), (HfTiO), (HfAIO) ‘ (La 2 O 3 ) or (LaAIO). 
     
     
         13 . The memory of  claim 11 , wherein said conductive carbon includes nano carbon tube. 
     
     
         14 . A memory comprising:
 pluralities of bit lines formed over a semiconductor substrate;   pluralities of word lines formed over said semiconductor substrate and perpendicular to said pluralities of bit lines forming with intercrossing areas and non-intercrossing areas;   at least one conductive carbon located at one of said non-intercrossing areas to define digital status.   
     
     
         15 . The memory of  claim 14 , wherein further comprising gate dielectric layer under said pluralities of word lines. 
     
     
         16 . The memory of  claim 15 , wherein said gate dielectric layer includes (SiO 2 ), (HfO 2 ), (ZrO 2 ), (TiO 2 ), (HfTiO), (HfAIO) ‘ (La 2 O 3 ) or (LaAIO). 
     
     
         17 . The memory of  claim 14 , wherein said conductive carbon includes nano carbon tube.

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