Integration Scheme for Dual Work Function Metal Gates

Abstract

A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. The method includes an independent work function adjustment process that implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants Lanthanide series dopants into a gate polysilicon layer of NMOS.

1 . A method for making a transistor, comprising:
 providing a semiconductor substrate containing a partial transistor, containing:
 a gate dielectric coupled to said semiconductor substrate; 
 a gate electrode coupled to said gate dielectric; 
 a gate hardmask coupled to said gate electrode; 
 source/drain sidewalls coupled to said gate electrode; and 
 source/drain regions within said semiconductor substrate; 
   forming an etch stop layer over said semiconductor substrate;   forming a PMD isolation layer over said etch stop layer;   reducing a thickness of said PMD isolation layer to expose said etch stop layer that is located over said gate hardmask;   removing said exposed etch stop layer;   removing said gate hardmask; and   implanting dopants into said gate electrode.   
   
   
       2 . The method of  claim 1 , further comprising:
 removing remaining portions of said PMD isolation layer;   performing a gate silicide loop to form a gate silicide within said gate electrode.   
   
   
       3 . The method of  claim 2  wherein said gate silicide loop comprises:
 forming a metal layer over said semiconductor substrate;   performing a first anneal to create said gate silicide;   removing an un-reacted portion of said metal layer; and   performing a second anneal.   
   
   
       4 . The method of  claim 3  wherein said metal layer contains Ni. 
   
   
       5 . The method of  claim 1  wherein said gate electrode comprises polysilicon. 
   
   
       6 . The method of  claim 1  wherein said etch stop layer comprises Si 3 N 4 . 
   
   
       7 . The method of  claim 1  wherein said PMD isolation layer comprises TEOS. 
   
   
       8 . The method of  claim 1  further comprising the step of performing a source/drain silicide loop to form a source/drain silicide within said source/drain regions before said step of forming an etch stop layer. 
   
   
       9 . The method of  claim 2  further comprising:
 removing remaining portions of said etch stop layer; and   performing a source/drain silicide loop to form a source/drain silicide within said source/drain regions.   
   
   
       10 . The method of  claim 1  wherein said gate hardmask comprises SiO 2 . 
   
   
       11 . The method of  claim 1  wherein said dopants are selected from a group consisting of lanthanide elements. 
   
   
       12 . The method of  claim 1  wherein said dopants comprise Yb. 
   
   
       13 . The method of  claim 1  wherein said dopants comprise Yb and As. 
   
   
       14 . The method of  claim 11  wherein said transistor is an NMOS transistor 
   
   
       15 . The method of  claim 14  wherein said N MOS transistor has a work function of approximately 4.1 eV 
   
   
       16 . The method of  claim 1  wherein said dopants are selected from a group consisting of Group IIIa elements. 
   
   
       17 . The method of  claim 1  wherein said dopants comprise Ga. 
   
   
       18 . The method of  claim 1  wherein said dopants comprise Ga 2 O 3 . 
   
   
       19 . The method of  claim 16  wherein said transistor is a PMOS transistor. 
   
   
       20 . The method of  claim 19  wherein said PMOS transistor has a work function of approximately 5.0 eV. 
   
   
       21 . The method of  claim 1  further comprising the step of removing a portion of said gate electrode before said step of implanting dopants into said gate electrode. 
   
   
       22 . The method of  claim 8  wherein said source/drain silicide comprises NiSi 
   
   
       23 . The method of  claim 9  wherein said source/drain silicide comprises NiSi 
   
   
       24 . The method of  claim 3  further comprising the step of forming a cap layer over said metal layer prior to said step of performing a first silicide anneal. 
   
   
       25 . The method of  claim 24  wherein said cap layer comprises titanium nitride. 
   
   
       26 . The method of  claim 3  wherein said gate silicide is a self-aligned silicide and said gate electrode is fully silicided by said second anneal. 
   
   
       27 . The method of  claim 1  wherein said partial transistor includes extension regions within said semiconductor substrate. 
   
   
       28 . A method for making PMOS and NMOS transistors, comprising:
 providing a semiconductor substrate containing partial PMOS and NMOS transistors, each containing:
 a gate dielectric coupled to said semiconductor substrate; 
 a gate electrode coupled to said gate dielectric; 
 a gate hardmask coupled to said gate electrode; 
 source/drain sidewalls coupled to said gate electrode; and 
 source/drain regions within said semiconductor substrate; 
   forming an etch stop layer over said semiconductor substrate;   forming a PMD isolation layer over said etch stop layer;   reducing a thickness of said PMD isolation layer to expose said etch stop layer that is located over said gate hardmasks of said PMOS and NMOS transistors;   removing said exposed etch stop layer;   removing said gate hardmasks of said PMOS and NMOS transistors;   forming a first layer of photoresist over said semiconductor substrate, then patterning said first layer of photoresist to expose regions containing said PMOS transistors;   implanting p-type dopants into said gate electrodes of said PMOS transistors, said p-type dopants selected from a group consisting of Group IIIa elements;   removing said patterned first layer of photoresist;   forming a second layer of photoresist over said semiconductor substrate, then patterning said second layer of photoresist to expose regions containing said NMOS transistors;   implanting n-type dopants into said gate electrodes of said NMOS transistors, said n-type dopants selected from a group consisting of Lanthanide elements; and   removing said patterned second layer of photoresist.   
   
   
       29 . The method of  claim 28 , further comprising:
 removing remaining portions of said PMD isolation layer;   performing a gate silicide loop to form a gate silicide within said gate electrodes of said PMOS and NMOS transistors.   
   
   
       30 . The method of  claim 29  wherein said gate silicide loop comprises:
 forming a metal layer over said semiconductor substrate;   performing a first anneal to create said gate silicide;   removing an un-reacted portion of said metal layer; and   performing a second anneal.   
   
   
       31 . The method of  claim 30  wherein said metal layer contains Ni. 
   
   
       32 . The method of  claim 28  wherein said gate electrode of said PMOS and NMOS transistors comprises polysilicon. 
   
   
       33 . The method of  claim 28  wherein said etch stop layer of said PMOS and NMOS transistors comprises Si 3 N 4 . 
   
   
       34 . The method of  claim 28  wherein said PMD isolation layer comprises TEOS. 
   
   
       35 . The method of  claim 28  further comprising the step of performing a source/drain silicide loop to form a source/drain silicide within said source/drain regions of said PMOS and NMOS transistors before said step of forming an etch stop layer. 
   
   
       36 . The method of  claim 29  further comprising:
 removing remaining portions of said etch stop layer; and   performing a source/drain silicide loop to form a source/drain silicide within said source/drain regions of said PMOS and NMOS transistors.   
   
   
       37 . The method of  claim 28  wherein said gate hardmask of said PMOS and NMOS transistors comprises SiO 2 . 
   
   
       38 . The method of  claim 28  further comprising the step of implanting As dopants into said gate electrodes of said NMOS transistors before said step of implanting n-type dopants into said gate electrodes of said NMOS transistors. 
   
   
       39 . The method of  claim 28  wherein said n-type dopant selected from a group consisting of Lanthanide elements is Yb. 
   
   
       40 . The method of  claim 28  wherein said gate dielectric of said NMOS transistor includes an lanthanide dopant. 
   
   
       41 . The method of  claim 40  wherein said lanthanide dopant is Yb. 
   
   
       42 . The method of  claim 28  further comprising the step of implanting oxygen into said gate electrodes of said PMOS transistors before said step of implanting p-type dopants into said gate electrodes of said PMOS transistors. 
   
   
       43 . The method of  claim 28  wherein said p-type dopant selected from a group consisting of Group IIIa elements is Ga. 
   
   
       44 . The method of  claim 28  wherein said gate dielectric of said PMOS transistor includes a Group IIIa dopant. 
   
   
       45 . The method of  claim 44  wherein said Group IIIa dopant is Ga. 
   
   
       46 . The method of  claim 28  further comprising the step of removing a portion of said gate electrode of said PMOS transistor before said step of implanting p-type dopants into said gate electrodes of said PMOS transistors. 
   
   
       47 . The method of  claim 35  wherein said source/drain silicide comprises NiSi. 
   
   
       48 . The method of  claim 36  wherein said source/drain silicide comprises NiSi 
   
   
       49 . The method of  claim 28  wherein said partial PMOS and NMOS transistors include extension regions within said semiconductor substrate. 
   
   
       50 . An NMOS transistor, comprising:
 a semiconductor substrate;   a gate dielectric coupled to said semiconductor substrate;   a fully silicided gate electrode coupled to said gate dielectric; and   source/drain regions located within said semiconductor substrate;   wherein said fully silicided gate electrode of said NMOS transistor includes an lanthanide series dopant.   
   
   
       51 . The NMOS transistor of  claim 50  wherein said fully silicided gate electrode also includes an As dopant. 
   
   
       52 . The NMOS transistor of  claim 50  wherein said lanthanide series dopant is Yb. 
   
   
       53 . The NMOS transistor of  claim 50  wherein said gate dielectric includes an lanthanide series dopant. 
   
   
       54 . The NMOS transistor of  claim 53  wherein said lanthanide series dopant is Yb. 
   
   
       55 . A PMOS transistor, comprising:
 a semiconductor substrate;   a gate dielectric coupled to said semiconductor substrate;   a fully silicided gate electrode coupled to said gate dielectric;   source/drain regions located within said semiconductor substrate;   wherein said fully silicided gate electrode of said PMOS transistor includes a Group IIIa dopant.   
   
   
       56 . The PMOS transistor of  claim 55  wherein said fully silicided gate electrode also includes oxygen. 
   
   
       57 . The PMOS transistor of  claim 55  wherein said Group IIIa dopant is Ga. 
   
   
       58 . The PMOS transistor of  claim 55  wherein said gate dielectric includes a Group IIIa dopant. 
   
   
       59 . The PMOS transistor of  claim 58  wherein said Group IIIa dopant is Ga.