Memory circuit arrangement and method for the production thereof

Abstract

In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

1 . A memory circuit arrangement comprising:
 a cell array substrate;   a memory cell array contained in a memory circuit, the memory cell array comprising a plurality of memory cells and is carried by the cell array substrate;   a logic circuit substrate being a different substrate than the cell array substrate;   a decoding circuit of the memory circuit, the decoding circuit is carried by the cell array substrate or by the logic circuit substrate and the decoding circuit is coupled to the memory cell array; and   a control circuit carried by the logic circuit substrate, the control circuit directly controls the decoding circuit.   
   
   
       2 . The circuit arrangement as claimed in  claim 1 , further comprising:
 word lines coupled to the memory cell array and bit lines coupled to the memory cell array; and   the decoding circuit comprises at least one of a word line decoding circuit for selecting a word line and a bit line decoding circuit for selecting a bit line.   
   
   
       3 . The circuit arrangement as claimed in  claim 1 , further comprising a sense amplifier, the control circuit directly controls the sense amplifier. 
   
   
       4 . The circuit arrangement as claimed in  claim 1 , wherein at least one of:
 the cell array substrate has substrate surfaces which surround only the cell array substrate and not the logic circuit substrate on all sides; or   the memory cells are volatile or nonvolatile memory cells.   
   
   
       5 . The circuit arrangement as claimed in  claim 1 , wherein the control circuit controls sequences when erasing the content of the memory cell. 
   
   
       6 . The circuit arrangement as claimed in  claim 1 , wherein:
 at least one word line is connected to memory cells of a row of memory cells of the memory cell array;   at least one a bit line is connected to memory cells of a column of memory cells of the memory cell array; or   an electrically conductive connection is disposed between the cell array substrate and the logic circuit substrate for each word and bit line.   
   
   
       7 . The circuit arrangement as claimed in  claim 1 , wherein:
 a main area of the cell array substrate and a main area of the logic circuit substrate lie in two planes parallel to one another; or   the main area of the cell array substrate is situated transversely with respect to the main area of the logic circuit substrate.   
   
   
       8 . The circuit arrangement as claimed in  claim 1 , wherein the cell array substrate has substrate surfaces which surround only the cell array substrate and not the logic circuit substrate on all sides. 
   
   
       9 . The circuit arrangement as claimed in  claim 1 , wherein the memory circuit arrangement comprises a plurality of word and bit lines and an electrically conductive connection is disposed between the cell array substrate and the logic circuit substrate for each word and bit line. 
   
   
       10 . The circuit arrangement as claimed in  claim 1 , wherein the memory circuit is one of a ROM, an EEPROM, a DRAM or an SRAM. 
   
   
       11 . The circuit arrangement as claimed in  claim 10  wherein the memory cells of the EEPROM are floating gate cells. 
   
   
       12 . The circuit arrangement as claimed in  claim 1 , wherein the memory circuit is a flash EEPROM or a stand alone flash EEPROM. 
   
   
       13 . The circuit arrangement as claimed in  claim 12  wherein the memory cells of the EEPROM are floating gate cells.