Application processors and memory architecture for wireless applications

Abstract

In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system.

1 . A mobile device, comprising: a memory sub-system comprising at least one of a volatile and a non-volatile memory an applications processor comprising at least one CPU;
 a baseband processor;   a memory sub-system coupled to the applications processor;   a display device wherein the applications processor comprises an arbitration mechanism for controlling access to the memory sub-system by the baseband and the at least one CPU, and an interface to the display device.   
   
   
       2 . The mobile device of  claim 1 , wherein comprises a frame buffer and a mechanism to update the display device from the frame buffer.
 The mobile device of  claim 1 , wherein the applications processor updates the display device based on a command from the baseband processor.   
   
   
       4 . The mobile device of  claim 1 , wherein the baseband processor accesses the memory sub-system by asserting a signal to the application processor 
   
   
       5 . The mobile device of  claim 1 , wherein the at least one of the CPU includes an instruction and data cache 
   
   
       6 . The mobile device of  claim 1 , wherein the application processor includes a write buffer 
   
   
       7 . The mobile device of  claim 1 , wherein at least one of the CPUs in the application processor operates a virtual machine 
   
   
       8 . The mobile device of  claim 7 , wherein the CPU operating the virtual machine executes Java byte codes 
   
   
       9 . The mobile device of  claims 8 , wherein a Java program counter and object references are shared between the base-band processor and the applications processor 
   
   
       10 . The mobile device of  claim 1 , wherein the application processor uses a clock to synchronize one or more indications asserted by the baseband processor to access the memory sub-system of the application processor 
   
   
       11 . The mobile device of  claim 10 , wherein a memory controller clock and a synchronizing clock are the same. 
   
   
       12 . The mobile device of  claim 2 , wherein the frame buffer is in the applications processor.