Semiconductor memory device and semiconductor integrated circuit device

Abstract

A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

1 - 12 . (canceled) 
   
   
       13 . A semiconductor integrated circuit device on a single semiconductor chip, comprising:
 a central processing unit; and   an internal memory operated between a power supply voltage and a reference potential and including:
 an input circuit coupled to the central processing unit, 
 a first memory mat, 
 a first input and output circuit coupled between the input circuit and the first memory mat, 
 a first switching transistor provided between the power supply voltage and the reference potential via the first input and output circuit, 
 a first power control circuit coupled to the first switching transistor and controlling an operation of the first switching transistor in response to a selection or a non-selection of the first memory mat, 
 a second switching transistor provided between the power supply voltage and the reference potential via the first power control circuit, 
 a third switching transistor provided between the power supply voltage and the reference potential via the input circuit, and 
 a second power control circuit coupled to the second and third switching transistors and controlling operations of the second and third switching transistors in response to a standby signal from the central processing unit. 
   
   
   
       14 . A semiconductor integrated circuit according to  claim 13 ,
 wherein the first switching transistor is turned on by the first power control circuit when the first memory mat is selected, and   wherein the first switching transistor is turned off by the first power control circuit when the first memory mat is unselected.   
   
   
       15 . A semiconductor integrated circuit according to  claim 14 ,
 wherein the second and third switching transistors are turned off by the second power control circuit when the second power control circuit receives the standby signal.   
   
   
       16 . A semiconductor integrated circuit according to  claim 13 ,
 wherein the second and third switching transistors are turned off by the second power control circuit when the second power control circuit receives the standby signal.   
   
   
       17 . A semiconductor integrated circuit, according to  claim 13 ,
 wherein the internal memory further includes:   a second memory mat,   a second input and output circuit coupled between the input circuit and the second memory mat,   a fourth switching transistor provided between the power supply voltage and the reference potential via the second input and output circuit,   a third power control circuit coupled to the fourth switching transistor and controlling an operation of the fourth switching transistor, and   a fifth switching transistor provided between the power supply voltage and the reference potential via the third power control circuit, an operation of the fifth switching transistor being controlled by the second power control circuit.   
   
   
       18 . A semiconductor integrated circuit according to  claim 17 ,
 wherein the fourth switching transistor is turned on by the third power control circuit when the second memory mat is selected, and   wherein the fourth switching transistor is turned off by the third power control circuit when the second memory mat is unselected.   
   
   
       19 . A semiconductor integrated circuit according to  claim 18 ,
 wherein the first switching transistor is turned on by the first power control circuit when the first memory mat is selected, and   wherein the first switching transistor is turned off by the first power control circuit when the first memory mat is unselected.   
   
   
       20 . A semiconductor integrated circuit according to  claim 19 ,
 wherein the second, third and fifth switching transistors are turned off by the second power control circuit when the second power control circuit receives the standby signal.   
   
   
       21 . A semiconductor integrated circuit device on a single semiconductor chip, comprising:
 a central processing unit; and   an internal memory operated between a power supply voltage and a reference potential and including:
 an input circuit coupled to the central processing unit, 
 a first memory mat, 
 a first input and output circuit coupled between the input circuit and the first memory mat, 
 a first switching transistor provided between the power supply voltage and the reference potential via the first input and output circuit, 
 a first power control circuit coupled to the first switching transistor and controlling an operation of the first switching transistor in response to a selection or a non-selection of the first memory mat, 
   a second switching transistor provided between the power supply voltage and the reference potential via the first power control circuit,   a second memory mat,   a second input and output circuit coupled between the input circuit and the second memory mat,   a third switching transistor provided between the power supply voltage and the reference potential via the second input and output circuit,   a second power control circuit coupled to the third switching transistor and controlling an operation of the third switching transistor,
 a fourth switching transistor provided between the power supply voltage and the reference potential via the second power control circuit, 
 a fifth switching transistor provided between the power supply voltage and the reference potential via the input circuit, and 
 a third power control circuit coupled to the second, fourth and fifth switching transistors and controlling operations of the second, fourth and fifth switching transistors in response to a standby signal from the central processing unit. 
   
   
   
       22 . A semiconductor integrated circuit according to  claim 21 ,
 wherein the first switching transistor is turned on by the first power control circuit when the first memory mat is in a selection state,   wherein the first switching transistor is turned off by the first power control circuit when the first memory mat is in a non-selection state,   wherein the third switching transistor is turned on by the second power control circuit when the second memory mat is in a selection state, and   wherein the third switching transistor is turned off by the second power control circuit when the second memory mat is in a non-selection state.   
   
   
       23 . A semiconductor integrated circuit according to  claim 22 ,
 wherein second, fourth and fifth switching transistors are turned off by the third power control circuit when the third power control circuit receives the standby signal.