Semiconductor chip package and method of manufacture

Abstract

A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

1 . A chip package comprising:
 a first chip unit comprising a first substrate and a first IC chip electrically connected to the first substrate through an opening in the first substrate;   a second chip unit mounted to the first chip unit and comprising a second substrate and a second IC chip electronically connected to the second substrate through an opening in the second substrate; and   a spacer maintaining a space between the first chip unit and the second chip unit.   
     
     
         2 . A chip package according to  claim 1 , wherein the spacer comprises an electrical conductor and electrically connects the first substrate and the second substrate. 
     
     
         3 . A chip package according to  claim 1 , wherein the spacer comprises a solder ball. 
     
     
         4 . A chip package according to  claim 1 , wherein each of the first substrate, the first IC chip, the second substrate and the second IC chip have first and second planar surfaces and the second planar surface of the first IC chip is mounted to the first planar surface of the first substrate and the second planar surface of the second IC chip is mounted to the first planar surface of the second substrate;
 wherein the second planar surface of the first substrate is mounted to the first planar surface of the second IC chip;   wherein the solder ball forming the spacer is formed on the first planar surface of the second substrate and the second planar surface of the first substrate; and   wherein the chip package further comprises other solder balls formed on the second planar surface of the second substrate to provide an external output.   
     
     
         5 . A chip package according to  claim 4 , wherein the other solder balls are electrically connected to the first and second IC chips. 
     
     
         6 . A chip package according to  claim 1 , wherein the first substrate and the first IC chip are electrically connected through bonding wire and the bonding wire is secured by an epoxy.