Oscillating divider topology

Abstract

An oscillator includes a first circuit that asynchronously generates an oscillating signal in response to a second circuit of the oscillator acknowledging each cycle of the oscillating signal.

1 . A frequency divider comprising:
 a first circuit to store a state of the divider; and   a second circuit to
 in response to an input signal having a first frequency, generate an output signal having a second frequency less than the first frequency, and 
 delay each change of the output signal until the state indicates stabilization of the first circuit in response to a prior change of the output signal. 
   
   
   
       2 . The frequency divider of  claim 1 , wherein the second circuit comprises:
 stages, each stage to provide at least one bit of the output signal.   
   
   
       3 . The frequency divider of  claim 2 , further comprising:
 at least one interlock device to regulate operation of one of the stages in response to a state of another one of the stages.   
   
   
       4 . The frequency divider of  claim 1 , wherein the second circuit encodes the output signal using 1 by n encoding. 
   
   
       5 . A method comprising:
 storing a state of a frequency divider;   in response to an input signal having a first frequency, generate an output signal having a second frequency less than the first frequency; and   delaying each change of the output signal until the state indicates stabilization of a circuit that stores a state of the divider in response to a prior change of the output signal.   
   
   
       6 . The method of  claim 5 , wherein the act of generating the output signal comprises:
 providing stages; and   using each stage to provide at least one bit of the output signal.   
   
   
       7 . The method of  claim 6 , further comprising:
 regulating operation of one of the stages in response to a state of another one of the stages.   
   
   
       8 . The method of  claim 5 , further comprising:
 encoding the output signal using 1 by n encoding.