Digital signal processor

Abstract

A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.

1 . A digital signal processor for performing a series of filtering calculations comprising:
 a data storage including a plurality of storage areas each of which is used for one of the series of filtering calculations and stores data in a rewritable manner;   an instruction memory for storing a plurality of instructions indicating at least filtering calculations on the data that are read from the data storage to be performed step by step, and outputting one of the plurality of instructions therefrom step by step, wherein each of the plurality of instructions includes a filter selection signal for indicating a type of filtering calculation that is to be performed in a corresponding step;   an operation circuit for performing the filtering calculations step by step, in accordance with each of the instructions output from the instruction memory; and   an initialization circuit including a logic circuit and a write circuit, wherein a memory initialization enable signal and a certain filter selection signal are provided to the logic circuit to drive the write circuit to compulsorily write a logic ‘0’ into a certain storage area in the data storage which is used for a certain type of filtering calculation when the instruction memory outputs a certain instruction including the certain filter selection signal for indicating the certain type of filtering calculation from among the plurality of instructions.   
     
     
         2 . A digital signal processor according to  claim 1 , wherein the data storage is a working RAM having an input terminal, an address terminal, a write-enable terminal, and an output terminal. 
     
     
         3 . A digital signal processor according to  claim 2 , wherein the write circuit comprises a first circuit for inputting the logic ‘0’ into the input terminal, and a second circuit for supplying a write-enable signal to the write-enable terminal.