Method and apparatus for dark current and hot pixel reduction in active pixel image sensors

Abstract

A method of operating an imager pixel that includes the act of applying a relatively small voltage on the gate of a transfer transistor during a charge acquisition period. If a small positive voltage is applied, a depletion region is created under the transfer transistor gate, which creates a path for dark current electrons to be transferred to a pixel floating diffusion region. The dark electrons are subsequently removed by a pixel reset operation. If a small negative voltage is applied to the transfer gate, electrons that would normally create dark current problems will instead recombine with holes thereby substantially reducing dark current.

1 . A method of operating an imager pixel circuit comprising a photosensor, transfer gate and a floating diffusion region, said method comprising the act of:
 applying a non-zero positive voltage to the transfer gate during a charge acquisition period for the photosensor.   
     
     
         2 . The method of  claim 1 , wherein the voltage is applied to the transfer gate for the entirety of the acquisition period. 
     
     
         3 . The method of  claim 1 , wherein the voltage is applied to the transfer gate for a portion of the acquisition period. 
     
     
         4 . The method of  claim 1 , further comprising the act of determining a gain setting of the pixel circuit, wherein a level of the applied voltage is based on the gain setting. 
     
     
         5 . A method of operating an imager pixel circuit comprising a photosensor, a transfer gate and a floating diffusion region, said method comprising the acts of:
 initiating a charge acquisition period for the photosensor; and   creating a depletion region underneath the transfer gate during the acquisition period by applying a positive voltage to the transfer gate, wherein the depletion region serves as a path for dark current electrons to flow to the floating diffusion region.   
     
     
         6 . The method of  claim 5 , wherein said positive voltage is applied during the entirety of the acquisition period. 
     
     
         7 . The method of  claim 5 , wherein said positive voltage is applied during a portion of the acquisition period. 
     
     
         8 . The method of  claim 5 , wherein a level of the positive voltage is dependent of a gain setting of the pixel circuit. 
     
     
         9 . A method of operating an imager pixel circuit comprising a photosensor, a transfer gate and a floating diffusion region, said method comprising the acts of:
 initiating a charge acquisition period for the photosensor; and   combining dark electrons underneath the transfer gate with electron holes to substantially reduce a number of dark current electrons by applying a positive voltage to the transfer gate during the charge acquisition period.   
     
     
         10 . The method of  claim 9 , wherein the voltage is applied during the entirety of the acquisition period. 
     
     
         11 . The method of  claim 9 , wherein the voltage is applied during a portion of the acquisition period. 
     
     
         12 . An imager comprising:
 an array of pixels, each pixel comprising a photosensor, transfer gate and a floating diffusion region; and   a control circuit electrically connected to said array, said control circuit configured to operate each pixel in a selected row by initiating a charge acquisition period for the photosensor, and configured to apply a positive voltage to the transfer gate of each pixel in the selected row during the acquisition period.   
     
     
         13 . The imager of  claim 12 , wherein the voltage is applied to the transfer gate for the entirety of the acquisition period. 
     
     
         14 . The imager of  claim 12 , wherein the voltage is applied to the transfer gate for a portion of the acquisition period. 
     
     
         15 . The imager of  claim 12 , wherein the positive voltage is greater than approximately 0.0 volts, but no more than approximately 0.8 volts. 
     
     
         16 . The imager of  claim 12 , wherein said control circuit further controls the pixel by resetting the floating diffusion region after the acquisition period. 
     
     
         17 . The imager of  claim 12 , wherein a level of the positive voltage is based on a gain setting of the imager. 
     
     
         18 . The imager of  claim 12 , wherein said imager is part of an image processing system. 
     
     
         19 . The imager of  claim 21 , wherein said imager is part of a camera system. 
     
     
         20 . An imager comprising:
 an array of pixels, each pixel comprising a photosensor, a transfer gate and a floating diffusion region; and   a control circuit electrically connected to said array, said control circuit configured to operate each pixel in a selected row by initiating a charge acquisition period for the photosensor, and applying a positive voltage to the transfer gate of each pixel in the selected row during the acquisition period, wherein a level of the voltage is based on a gain setting of the imager.   
     
     
         21 . The imager of  claim 20 , further comprising means for determining the gain setting of the imager. 
     
     
         22 . The imager of  claim 20 , wherein if the gain setting is below a predefined threshold, the control circuit is configured to apply a ground potential to the transfer gate during the acquisition period. 
     
     
         23 . The imager of  claim 20 , wherein said imager is part of an image processing system. 
     
     
         24 . The imager of  claim 20 , wherein said imager is part of a camera system. 
     
     
         25 . An active pixel comprising:
 a light sensing element formed in a semiconductor substrate; and   a transfer transistor formed between said light sensing element and a floating node and selectively operative to transfer a signal from said light sensing element to said floating node, wherein said transfer transistor is positively biased during an integration period during a first mode of operation.   
     
     
         26 . The pixel of  claim 25 , wherein said light sensing element is selected from the group of photodiode, pinned photodiode, partially pinned photodiode, or photogate. 
     
     
         27 . The pixel of  claim 25 , wherein said transfer transistor is turned off during said integration period during a second mode of operation. 
     
     
         28 . The pixel of  claim 25 , wherein said first mode of operation is used if a level of incident light is low. 
     
     
         29 . The pixel of  claim 27 , wherein said second mode of operation is used if a level of incident light is normal. 
     
     
         30 . The pixel of  claim 25 , further including an amplification transistor controlled by said floating node, wherein said amplification transistor outputs an amplified version of said signal to a column bitline. 
     
     
         31 . The pixel of  claim 25 , further including a reset transistor operative to reset said floating node to a reference voltage. 
     
     
         32 . The pixel of  claim 25 , wherein said transfer transistor is positively biased such that it is partially turned on during said integration period. 
     
     
         33 . The pixel of  claim 25  wherein said pixel is integrated into a CMOS image sensor. 
     
     
         34 . The pixel of  claim 25  wherein said pixel is part of a 4T, 5T, 6T, or 7T pixel architecture. 
     
     
         35 . A method of operating a pixel of an image sensor, said pixel including a light sensing element, a transfer transistor between said light sensing element and a floating node for transferring a signal from said light sensing element to said floating node, and an amplification transistor modulated by said signal on said floating node, the method comprising:
 determining a level of incident light;   if said level of illumination is low:   partially turning on said transfer transistor during an integration period; and   if said level of illumination is normal:   substantially turning off said transfer transistor during said integration period.   
     
     
         36 . The method of  claim 35  wherein said light sensing element is selected from the group of photodiode, pinned photodiode, partially pinned photodiode, or photogate. 
     
     
         37 . The method of  claim 35  wherein said amplification transistor outputs an amplified version of said signal to a column bitline. 
     
     
         38 . The method of  claim 35  wherein said pixel further includes a reset transistor operative to reset said floating node to a reference voltage. 
     
     
         39 . An active pixel comprising:
 a light sensing element formed in a semiconductor substrate; and   a transfer transistor formed between said light sensing element and a floating node and selectively operative to transfer a signal from said light sensing element to said floating node, wherein said transfer transistor is positively biased such that said transfer transistor is partially turned on during an integration period and substantially fully turned on during a readout period during a first mode of operation.   
     
     
         40 . The pixel of  claim 39 , wherein said light sensing element is selected from the group of photodiode, pinned photodiode, partially pinned photodiode, or photogate. 
     
     
         41 . The pixel of  claim 39 , wherein said transfer transistor is turned off during said integration period during a second mode of operation. 
     
     
         42 . The pixel of  claim 39 , wherein said first mode of operation is used if a level of incident light is low. 
     
     
         43 . The pixel of  claim 41 , wherein said second mode of operation is used if a level of incident light is normal. 
     
     
         44 . The pixel of  claim 39  further including an amplification transistor controlled by said floating node, wherein said amplification transistor outputs an amplified version of said signal to a column bitline. 
     
     
         45 . The pixel of  claim 39  further including a reset transistor operative to reset said floating node to a reference voltage. 
     
     
         46 . The pixel of  claim 39  wherein said transfer transistor is positively biased such that it is partially turned on during said integration period. 
     
     
         47 . The pixel of  claim 39  wherein said pixel is integrated into a CMOS image sensor. 
     
     
         48 . The pixel of  claim 39  wherein said pixel is part of a 4T, 5T, 6T, or 7T pixel architecture.