Sram circuitry

Abstract

A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

1 . A method for writing data into a static ram cell, the method comprising:
 setting a wordline of the static ram cell to a first reference voltage, the wordline providing the current for writing data into the cell, the cell having true and complement bit lines, the bit line having a conductive path to the wordline and the complement bit line having a non-conductive path to the wordline;   connecting the bit line via a first switch and the complement bit line via a second switch to a second reference voltage; and   pulsing the bit line of the cell to the first reference voltage during a short time interval to write new data into the cell, such that the complement bit line has a conductive path to the wordline.   
   
   
       2 . A method for retaining data in a static ram cell, the method comprising setting a wordline of the static ram cell to a voltage that provides leakage currents to the cell, the cell having true and complement bit lines, the bit line having a conductive path for carrying the leakage currents from the wordline and the complement bit line having a non-conductive path to the wordline. 
   
   
       3 . A method for retaining data in a static ram cell as recited in  claim 2 ,
 wherein the true and complement bit lines have been set to a particular voltage; and   wherein the voltage of the wordline is more than one threshold voltage above the particular voltage on the true and complement bit lines.   
   
   
       4 . A method for retaining data in a static ram cell as recited in  claim 2 , further comprising
 detecting current flow in the non-conductive path to the wordline; and   recording the detected current flow in a latching detector, the latching detector indicating a strike event at the cell.