Data processor

Abstract

A data processor arranged so that a block transfer control unit ( 12 ) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory ( 5 ) and an external memory ( 25,26 ). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

1 - 20 . (canceled) 
   
   
       21 . A data processor comprising:
 processing means;   first storage means accessible by said processing means;   access control means for responding to a particular access request issued by said processing means to control a block transfer, in which said first storage means is used as a first transfer object;   cache memory means coupled to a first bus which is coupled to said processing means, said first storage means, and said access control means; and   bus interface control means connected to said access control means and configured to perform interface control for a second transfer object,   wherein a set of instructions for said processing means includes a particular instruction for making said processing means issue the particular access request, the particular instruction having an address field and including a first cache memory operating instruction,   wherein when an address specified by the address field is a logical address mapped to said first storage means, the address is set as one of a transfer source address or a transfer destination address of the block transfer, and   a transfer source address or transfer destination address for said second transfer object of the block transfer is a physical address corresponding to a logical address of said address field,   said first storage means being assigned a cache non-object address for said cache memory means, and   wherein when the logical address specified by the address field directs a cache object address for said cache memory means, the first cache memory-operating instruction causes said cache memory means to retain data of a second storage means associated with the physical address corresponding to the different logical address, at a cache object address specified by the logical address.   
   
   
       22 . The data processor of  claim 21 , wherein the particular instruction also includes a second cache memory-operating instruction, and
 wherein when the logical address specified by the address field directs a cache object address and a cache hit is detected at a data location specified by the logical address and a cache entry associated with the cache hit is dirty, the second cache memory-operating instruction causes an operation of writing back to the second storage means.   
   
   
       23 . The data processor of  claim 22 , wherein the particular instruction has an operation code identical to an operation code of the second cache memory-operating instruction, and sets the cache non-object address of the address field as the source address. 
   
   
       24 . The data processor of  claim 21 , wherein the particular instruction has an operation code identical to an operation code of the first cache memory-operating instruction, and sets the cache non-object address of the address field as the destination address. 
   
   
       25 . The data processor of  claim 21 , wherein said access control means performs memory control in regard to a cache hit and a cache miss with respect to said cache memory means.