Field effect transistor having germanium nanorod and method of manufacturing the same

Abstract

A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

1 . A field effect transistor, comprising:
 a gate oxide layer on a silicon substrate:   at least one Ge nanorod embedded in the gate oxide layer having both ends thereof exposed;   a source electrode and a drain electrode connected to opposite sides of the Ge nanorod; and   a gate electrode on the gate oxide layer between the source electrode and the drain electrode.   
     
     
         2 . The field effect transistor of  claim 1 , wherein the at least one Ge nanorod comprises 2 to 5 nanorods separated from each other. 
     
     
         3 . The field effect transistor of  claim 1 , wherein the at least one Ge nanorod has a diameter of about 1 to about 20 nm. 
     
     
         4 . The field effect transistor of  claim 1 , wherein the at least one Ge nanorod in a channel region has a circular or an oval cross-section. 
     
     
         5 . The field effect transistor of  claim 1 , wherein the source electrode and the drain electrode form a Schottky barrier junction with the at least one Ge nanorod. 
     
     
         6 . The field effect transistor of  claim 5 , wherein the source electrode and the drain electrode are formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er. 
     
     
         7 . The field effect transistor of  claim 1 , wherein the gate oxide layer is a dielectric layer having a dielectric constant higher than that of silicon oxide. 
     
     
         8 . The field effect transistor of  claim 7 , wherein the gate oxide layer is formed of one selected from the group consisting of Si 3 N 4 , Ta 2 O 5 , HfO 2 , Zr 2 O 5 , Al 2 O 3 , HfO x N y , HfSiO, and HfSiON. 
     
     
         9 . The field effect transistor of  claim 8 , wherein the gate electrode comprises:
 a first metal layer formed of one selected from Ta, TaN, and TiN; and   a second metal layer formed of polysilicon on the first metal layer.   
     
     
         10 . A method of manufacturing a field effect transistor, the method comprising:
 forming an insulating layer and a first silicon layer on a silicon substrate;   sequentially forming a SiGe layer and a second silicon layer on the first silicon layer;   forming silicon oxide layers by oxidizing the first and second silicon layers and Si of the SiGe layer on the silicon substrate, and forming at least one Ge nanorod from the SiGe layer;   forming a source electrode and a drain electrode contacting opposite ends of the at least one Ge nanorod;   forming a gate oxide layer that surrounds the at least one Ge nanorod in a region for forming a channel region between the source electrode and the drain electrode; and   forming a gate electrode on the gate oxide layer.   
     
     
         11 . The method of  claim 10 , wherein the sequentially forming of the SiGe layer and the second silicon layer is repeated 2 to 5 times on the first silicon layer. 
     
     
         12 . The method of  claim 10 , wherein the insulating layer is formed of a material having an etching rate different from that of the silicon oxide layers. 
     
     
         13 . The method of  claim 10 , wherein forming the source electrode and the drain electrode comprises:
 forming a first photoresist in the region for forming the channel region;   exposing both ends of the at least one Ge nanorod by removing the silicon oxide layers in regions for forming the source electrode and the drain electrode; and   depositing a metal having a work function greater than that of Ge in the regions for forming the source electrode and the drain electrode.   
     
     
         14 . The method of  claim 10 , wherein forming the gate oxide layer comprises:
 exposing the at least one Ge nanorod by removing the silicon oxide layers in the region for forming the channel region; and   forming the gate oxide layer that surrounds the at least one Ge nanorod using a material having a dielectric constant higher than that of silicon oxide.   
     
     
         15 . The method of  claim 14 , further comprising:
 forming a cross-section of the at least one Ge nanorod in the channel region into a circle or an oval shape by annealing the silicon substrate in a H 2  or D 2  atmosphere prior to forming the gate oxide layer.   
     
     
         16 . The method of  claim 14 , wherein the material is one selected from the group consisting of Si 3 N 4 , Ta 2 O 5 , HfO 2 , Zr 2 O 5 , Al 2 O 3 , HfO x N y , HfSiO, and HfSiON. 
     
     
         17 . The method of  claim 16 , wherein the forming of the gate electrode comprises forming a first metal layer formed of one selected from Ta, TaN, and TiN and forming a second metal layer formed of polysilicon on the first metal layer. 
     
     
         18 . The method of  claim 10 , wherein the SiGe layer has a composition of Si 1-x Ge x , where 0.1<x<0.5. 
     
     
         19 . The method of  claim 10 , wherein the source electrode and the drain electrode are formed of a metal selected from the group consisting of Pt, Ni, Co, V, Yb, and Er. 
     
     
         20 . The method of  claim 10 , wherein the gate oxide layer is formed of silicon oxide, and the forming of the gate electrode comprises forming a polysilicon layer. 
     
     
         21 . The method of  claim 10 , wherein the at least one Ge nanorod has a diameter of about 1 to about 20 nm.