CMOS image sensor and manufacturing method thereof

Abstract

A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only in a peripheral circuit.

1 - 5 . (canceled) 
   
   
       6 . A CMOS image sensor comprising:
 a semiconductor substrate;   gate spacers formed on the semiconductor substrate;   a gate insulation layer with a high dielectric constant formed between the gate spacers and on the semiconductor substrate after removing a dummy gate stack formed between the gate spacers;   a gate electrode formed between the gate spacers and on the gate insulation layer with a high dielectric constant;   a silicide layer formed on the gate electrode; and   a source/drain region formed in the semiconductor substrate at a position exterior to the gate.   
   
   
       7 . The CMOS image sensor of  claim 6 , wherein the gate insulation layer is formed between the gate spacers after the source/drain region is formed. 
   
   
       8 . The CMOS image sensor of  claim 6 , wherein the removal of the dummy gate stack is performed after the source/drain region is formed. 
   
   
       9 . The CMOS image sensor of  claim 7 , wherein the removal of the dummy gate stack is performed after the source/drain region is formed. 
   
   
       10 . The CMOS image sensor of  claim 6 , wherein the CMOS image sensor includes a peripheral circuit region and a pixel region, wherein the CMOS image sensor further comprises a silicide layer formed on the source/drain region in the peripheral circuit region but not in the pixel region. 
   
   
       11 . The CMOS image sensor of  claim 6 , wherein the gate insulation layer with a high dielectric constant is formed at a temperature under 600° C. 
   
   
       12 . A CMOS image sensor comprising:
 a semiconductor substrate having a pixel region and a peripheral circuit region;   gate spacers formed on the semiconductor substrate of the pixel region and the peripheral circuit region;   a gate insulation layer formed on the semiconductor substrate between the gate spacers;   a gate electrode formed on the gate insulation layer between the gate spacers;   a source/drain region formed in the semiconductor of the pixel region and the peripheral circuit region;   a silicide layer formed on the gate electrode in both the pixel region and the peripheral circuit region, and on the source/drain region formed in the semiconductor of the peripheral circuit region   
   
   
       13 . The CMOS image sensor of  claim 12 , wherein the CMOS image sensor further comprises a lightly doped drain (LDD) structure in the pixel region and in the peripheral region. 
   
   
       14 . The CMOS image sensor of  claim 12 , wherein the gate insulation layer is a insulation layer with a high dielectric constant. 
   
   
       15 . The CMOS image sensor of  claim 12 , wherein the gate electrode is polysilicon.