Planar interconnect structure for hybrid circuits

Abstract

Described herein is an electronic device in which one or more planar interconnect structure are interposed between two substrates each incorporating a hybrid circuit. The planar interconnect structure has a plurality of conductive traces formed on one of its faces for electrically connecting sets of interconnection points of each of the hybrid circuits.

1 . An electronic device, comprising:
 a first substrate;   a plurality of first electronic components disposed on at least a first side or a second side of the first substrate forming a first hybrid circuit,   a first set of interconnect points disposed on the first side of the first substrate and electrically connected with the first hybrid circuit;   a second substrate;   a plurality of second electronic components disposed on at least a first side or a second side of the second substrate forming a second hybrid circuit,   a second set of interconnect points disposed on the first side of the second substrate and electrically connected with the second hybrid circuit;   one or more planar interconnect structures, each having a plurality of conductive traces formed on one of its faces that traverse between two opposite edges of the planar interconnect structure leaving exposed ends of the conductive traces on the two opposite edges;   wherein one or more of the planar interconnect structures are disposed between the first sides of the first and second substrates with the two opposite edges of the planar interconnect structure contacting the first sides of the first and second substrates such that the exposed ends of the conductive traces are aligned with the first and second sets of interconnection points to form conductive paths therebetween and electrically connect the first and second hybrid circuits.   
     
     
         2 . The device of  claim 1  wherein the conductive traces of the planar interconnect structure are formed by coating a face of the planar structure with a conductive material and then etching away selected portions of the coating to form the separate conductive traces. 
     
     
         3 . The device of  claim 1  wherein the conductive traces of the planar interconnect structure are formed by forming a plurality of grooves on a face of the planar section that traverse from one edge to the other and then filling the grooves by printing a conductive material to form the conductive traces. 
     
     
         4 . The device of  claim 1  wherein the one or more planar interconnect structures and the sets of interconnect points are disposed toward peripheral edges of the first and second substrates. 
     
     
         5 . The device of  claim 4  wherein:
 one or more of the first electronic components are disposed on the first side of the first substrate and/or one or more of the second electronic components are disposed on the first side of the second substrate; and,   the dimensions of the one or more planar interconnect structures are such that the space between the first and second substrates is sufficient to accommodate the first and/or second electronic components located therein.   
     
     
         6 . The device of  claim 1  further comprising bonding means for bonding the exposed ends of the conductive traces to the sets of interconnection points. 
     
     
         7 . The device of  claim 6  wherein said bonding means is a solder joint formed by a reflow solder technique. 
     
     
         8 . The device of  claim 6  wherein said bonding means is a conductive epoxy joint formed by a conductive epoxy attachment technique. 
     
     
         9 . The device of  claim 1  wherein the planar interconnect structure further comprises first and second planar sections with the face of the first planar section having the conductive traces formed thereon and with the face of the second planar section bonded to the face of the first planar section to cover the conductive traces and leave the ends of the conductive traces exposed at the opposite edges of the planar interconnect structure. 
     
     
         10 . The device of  claim 1  further comprising encapsulating material for filling the space between the first and second substrates and for encasing the first and second hybrid circuits and planar interconnect structures to form a monolithic component. 
     
     
         11 . A method for constructing an electronic device, comprising:
 disposing a plurality of first electronic components on at least a first side or a second side of a first substrate to form a first hybrid circuit,   disposing a first set of interconnect points on the first side of the first substrate and electrically connected with the first hybrid circuit;   disposing a plurality of second electronic components on at least a first side or a second side of a second substrate to form a second hybrid circuit,   disposing a second set of interconnect points on the first side of the second substrate and electrically connected with the second hybrid circuit;   done or more planar interconnect structures, each having a plurality of conductive traces formed on one of its faces that traverse between two opposite edges of the planar interconnect structure leaving exposed ends of the conductive traces on the two opposite edges;   disposing one or more planar interconnect structures between the first sides of the first and second substrates, each planar interconnect structure having a plurality of conductive traces formed on one of its faces that traverse between two opposite edges of the planar interconnect structure leaving exposed ends of the conductive traces on the two opposite edges, wherein the two opposite edges of the planar interconnect structure contact the first sides of the first and second substrates such that the exposed ends of the conductive traces are aligned with the first and second sets of interconnection points to form conductive paths therebetween and electrically connect the first and second hybrid circuits.   
     
     
         12 . The method of  claim 11  further comprising coating a face of the planar interconnect structure with a conductive material and then etching away selected portions of the coating to form the separate conductive traces. 
     
     
         13 . The method of  claim 11  further comprising forming a plurality of grooves on a face of the planar section that traverse from one edge to the other and then filling the grooves by printing a conductive material to form the conductive traces. 
     
     
         14 . The method of  claim 11  further comprising disposing the one or more planar interconnect structures and the sets of interconnect points toward peripheral edges of the first and second substrates. 
     
     
         15 . The method of  claim 14  further comprising:
 disposing one or more of the first electronic components on the first side of the first substrate and/or disposing one or more of the second electronic components on the first side of the second substrate; and,   wherein the dimensions of the one or more planar interconnect structures are such that the space between the first and second substrates is sufficient to accommodate the first and/or second electronic components located therein.   
     
     
         16 . The method of  claim 11  further comprising bonding the exposed ends of the conductive traces to the sets of interconnection points. 
     
     
         17 . The method of  claim 16  wherein the bonding is performed with a solder joint formed by a reflow solder technique. 
     
     
         18 . The method of  claim 16  wherein the bonding is performed with a conductive epoxy joint formed by a conductive epoxy attachment technique. 
     
     
         19 . The method of  claim 11  further comprising:
 forming the planar interconnect structure with first and second planar sections;   forming the conductive traces on the face of the first planar section; and,   bonding the face of the second planar section to the face of the first planar section to cover the conductive traces and leave the ends of the conductive traces exposed at the opposite edges of the planar interconnect structure.   
     
     
         20 . The method of  claim 11  further comprising filling the space between the first and second substrates with encapsulating material and encasing the first and second hybrid circuits and planar interconnect structures to form a monolithic component.