System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards

Abstract

Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.

1 .- 8 . (canceled) 
     
     
         9 . An information handling system comprising:
 a circuit board operable to support electronic components, the circuit board having a surface plane, a power plane and a ground plane;   an electronic component socket coupled to the circuit board surface plane;   plural wirelines disposed in the circuit board and interfaced with the socket, the wirelines operable to communicate signals with the socket;   an electronic component coupled to the socket and operable to process information for communication as signals through the socket and wirelines, the electronic component operating with parasitic inductance and capacitance;   one or more power vias interfacing the socket to the power plane; and   one or more ground vias interfacing the socket to the ground plane;   wherein the power vias and ground vias are configured according to one or more factors associated with increased parasitic capacitance that offsets the effects of the parasitic inductance.   
     
     
         10 . The information handling system of  claim 9  wherein the one or more factors comprise the radius associated with the equivalent line charge of the power via. 
     
     
         11 . The information handling system of  claim 9  wherein the one or more factors comprise the distance associated with the line charges between a power via and a ground via. 
     
     
         12 . The information handling system of  claim 9  wherein the one or more factors comprise the length of one or more of the vias. 
     
     
         13 . The information handling system of  claim 9  wherein the electronic component comprises a processor packaged with ball grid array connectors and the socket comprises a ball grid array socket configured to accept the processor. 
     
     
         14 . The information handling system of  claim 9  further comprising one or more buried vias integrated within the circuit board and interfaced with the ground plane, the buried via disposed to according to the one or more factors to increase parasitic capacitance. 
     
     
         15 . The information handling system of  claim 14  wherein the buried via at least partially encircles a power via. 
     
     
         16 . The information handling system of  claim 14  wherein the buried via at least partially encircles a via associated with communication of a signal. 
     
     
         17 .- 20 . (canceled)