Display System Having Floating Point Rasterization and Floating Point Framebuffering

Abstract

A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

1 . A rendering circuit comprising:
 a geometry processor;   a rasterizer coupled to the geometry processor, the rasterizer comprising a scan converter having an input and an output, the scan converter being configured to scan convert data received at the input, at least a portion of the data received at the input being in floating point format, the scan converter being configured to output data from the output, at least a portion of the data from the output being floating point data; and   a frame buffer coupled to the rasterizer for storing a plurality of color values in floating point format.   
     
     
         2 . The rendering circuit as defined by  claim 1  wherein the scan converter is configured to scan convert on an entirely floating point basis. 
     
     
         3 . The rendering circuit as defined by  claim 1  wherein the data received at the input comprises color data. 
     
     
         4 . The rendering circuit as defined by  claim 1  wherein the rasterizer further includes a floating point texture circuit. 
     
     
         5 . The rendering circuit as defined by  claim 1  wherein the rasterizer further includes a floating point texture memory. 
     
     
         6 . The rendering circuit as defined by  claim 1  wherein the rasterizer further includes a floating point fog circuit. 
     
     
         7 . The rendering circuit as defined by  claim 1  wherein the rasterizer further includes a floating point blender. 
     
     
         8 . The rendering circuit as defined by  claim 1  wherein the rasterizer further includes a floating point lighting circuit. 
     
     
         9 . The rendering circuit as defined by  claim 1  wherein the rasterizer operates entirely on a floating point basis. 
     
     
         10 . The rendering circuit as defined by  claim 1  further comprising a circuit board coupled with the geometry processor, rasterizer, and frame buffer. 
     
     
         11 . A rendering circuit comprising:
 a rasterizer for performing a rasterization process, at least a portion of the rasterization process performed in a floating point format; and   a floating point frame buffer coupled to the rasterizer for storing a plurality of floating point color values.   
     
     
         12 . The rendering circuit as defined by  claim 11  wherein the floating point color values are read out from the frame buffer in the floating point format for display. 
     
     
         13 . The rendering circuit as defined by  claim 11  wherein the rasterization process is performed on an entirely floating point basis. 
     
     
         14 . The rendering circuit as defined by  claim 11  wherein the rasterizer comprises an input and an output, the rasterizer configured to process floating point data received at the input, the rasterizer configured to output floating point data at the output. 
     
     
         15 . The rendering circuit as defined by  claim 11  wherein the rasterizer includes a floating point texture circuit. 
     
     
         16 . The rendering circuit as defined by  claim 11  wherein the rasterizer includes a floating point texture memory. 
     
     
         17 . The rendering circuit as defined by  claim 11  wherein the rasterizer includes a floating point fog circuit. 
     
     
         18 . The rendering circuit as defined by  claim 11  wherein the rasterizer includes a floating point blender. 
     
     
         19 . The rendering circuit as defined by  claim 11  wherein the rasterizer includes a floating point lighting circuit. 
     
     
         20 . The rendering circuit as defined by  claim 11  wherein the rasterizer includes a floating point scan converter. 
     
     
         21 . The rendering circuit as defined by  claim 11  further comprising a circuit board coupled with the rasterizer and frame buffer. 
     
     
         22 . A rendering circuit comprising:
 a rasterizer including at least one of a floating point fog subsystem and a floating point texture subsystem; and   a frame buffer coupled to the rasterizer for storing a plurality of color values in the floating point format.   
     
     
         23 . The rendering circuit as defined by  claim 22  wherein the rasterizer comprises both the floating point fog subsystem and the floating point texture subsystem. 
     
     
         24 . The rendering circuit as defined by  claim 22  wherein the at least one floating point fog subsystem is configured to perform fog operations on an entirely floating point basis. 
     
     
         25 . The rendering circuit as defined by  claim 22  wherein the at least one floating point texture subsystem is configured to perform texture operations on an entirely floating point basis. 
     
     
         26 . The rendering circuit as defined by  claim 22  wherein the rasterizer comprises an input and an output, the rasterizer configured to process floating point data received at the input, the rasterizer configured to output floating point data at the output. 
     
     
         27 . The rendering circuit as defined by  claim 22  wherein the rasterizer further comprises at least one of a floating point blending subsystem and a floating point antialiasing subsystem. 
     
     
         28 . The rendering circuit as defined by  claim 22  further comprising texture memory configured to store texture data on a floating point basis. 
     
     
         29 . A rendering circuit comprising:
 a geometry processor configured to perform geometric calculations on a plurality of vertices of a three-dimensional primitive;   a rasterizer coupled with the geometry processor, the rasterizer comprising a first raster portion and a second raster portion, the first raster portion configured to translate three-dimensional primitives into a set of corresponding fragments or pixels, the second raster portion configured to fill-in the set of fragments or pixels, at least a portion of the second raster portion operating on a floating point basis; and   a floating point frame buffer coupled to the rasterizer for storing a plurality of floating point color values.   
     
     
         30 . The rendering circuit as defined by  claim 29  wherein the first raster portion operates on an entirely floating point basis. 
     
     
         31 . The rendering circuit as defined by  claim 29  wherein the second raster portion includes a floating point texture circuit. 
     
     
         32 . The rendering circuit as defined by  claim 29  wherein the second raster portion includes a floating point texture memory. 
     
     
         33 . The rendering circuit as defined by  claim 29  wherein the second raster portion includes a floating point fog circuit. 
     
     
         34 . The rendering circuit as defined by  claim 29  wherein the second raster portion includes a floating point blender. 
     
     
         35 . The rendering circuit as defined by  claim 29  wherein the second raster portion includes a floating point lighting circuit. 
     
     
         36 . The rendering circuit as defined by  claim 29  where the second raster portion operates entirely on a floating point basis. 
     
     
         37 . The rendering circuit as defined by  claim 29  where the second raster portion operates at least in part on a fixed point basis 
     
     
         38 . A rendering circuit comprising:
 means for performing geometric calculations on a plurality of vertices of a primitive; and   buffer means for storing a plurality of color values in the floating point format.   
     
     
         39 . The rendering circuit as defined by  claim 38  further comprising means for rasterizing the primitive at least partially on a floating point basis. 
     
     
         40 . The rendering circuit as defined by  claim 39  wherein the rasterizing means comprises means for filling fragments and pixels on an entirely floating point basis. 
     
     
         41 . The rendering circuit as defined by  claim 39  wherein the rasterizing means comprises means for scan converting on an entirely floating point basis. 
     
     
         42 . A rendering circuit comprising:
 a floating point frame buffer for storing a plurality of floating point color values, the floating point color values being written to, read from, and stored in the frame buffer using a specification of the floating point color values that corresponds to a level of range and precision.   
     
     
         43 . A rendering circuit comprising:
 a floating point frame buffer for storing a plurality of floating point color values, the frame buffer being configured so that floating point color values can be written to, read from, and stored in the frame buffer using a specification of the floating point color values that corresponds to a level of range and precision.   
     
     
         44 . The rendering circuit as defined by  claim 43  further comprising a read block configured to read floating point color values from the frame buffer. 
     
     
         45 . The rendering circuit as defined by  claim 43  further comprising a write block configured to write floating point color values to the frame buffer. 
     
     
         46 . The rendering circuit as defined by  claim 45  further comprising:
 a read block configured to read floating point color values from the frame buffer; and   a operation block configured to operate directly on floating point color values read from the frame buffer.   
     
     
         47 . The rendering circuit as defined by  claim 43  further comprising a rasterizer that at least partially operates on a floating point basis. 
     
     
         48 . In a rendering circuit, a method for operating on data stored in a frame buffer, the method comprising:
 storing the data in the frame buffer in a floating point format;   reading the data from the frame buffer in the floating point format; and   writing the data to the frame buffer in the floating point format,   writing, storing, and reading the data in the frame buffer in the floating point format further comprising a specification of the floating point format, wherein the specification corresponds to a level of range and precision.   
     
     
         49 . The method as defined by  claim 48  further comprising operating directly on the data in the floating point format. 
     
     
         50 . The method as defined by  claim 49  wherein storing is performed before reading, reading is performed before operating, and operating is performed before writing. 
     
     
         51 . The method as defined by  claim 48  wherein storing is performed before reading, reading being performed before writing. 
     
     
         52 . A rendering circuit comprising:
 a rasterizer for performing a rasterization process; and   a hardware floating point frame buffer coupled to the rasterizer for storing a plurality of floating point color values.   
     
     
         53 . The rendering circuit as defined by  claim 52  wherein the frame buffer and rasterizer are implemented on a single chip. 
     
     
         54 . The rendering circuit as defined by  claim 53  wherein at least a portion of the rasterization process is performed in a floating point format. 
     
     
         55 . The rendering circuit as defined by  claim 52  wherein the rasterizer and frame buffer form a dedicated rendering pipeline. 
     
     
         56 . The rendering circuit as defined by  claim 52  further comprising a block configured to read floating point color values from the frame buffer. 
     
     
         57 . The rendering circuit as defined by  claim 56  wherein the floating point color values are processed to produce processed floating point color values, the circuit further comprising a store block configured to store processed floating point color values in the frame buffer.