Wide window clock scheme for loading output fifo registers

Abstract

A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is automatically disabled. Initially, the circuit is reset such that one clock is active, and the other disabled. Upon receiving a valid READ command, a shift chain attached to the FICLK that is currently low begins counting the clock cycles. This eventually determines when the FICLK that is currently low can be enabled. The final enable is dependent upon the turning off the FICLK that is currently high. The FICLK that is enabled during the reset turns off a fixed delay after the falling edge of the YCLK associated with the READ command.

1 . An integrated circuit memory comprising:
 a plurality of memory banks coupled to a first data bus;   a second data bus coupled to the first data bus;   a first input access device for coupling the second data bus to a first FIFO register;   a first output access device for coupling the first FIFO register to an I/O pad;   a second input access device for coupling the second data bus to a second FIFO register; and   a second output access device for coupling the second register to the I/O pad,   wherein the first and second input access devices receive first and second FIFO clock signals, the first and second output access devices receive first and second output clock signals, and wherein the phase and duty cycle of the FIFO clock signals are variable to provide the widest possible window for capturing data and preventing run-through in the first and second FIFO registers.