US2008286925A1PendingUtilityA1

Nonvolatile memory with backplate

40
Assignee: WALKER ANDREW JPriority: May 15, 2007Filed: May 27, 2008Published: Nov 20, 2008
Est. expiryMay 15, 2027(~0.8 yrs left)· nominal 20-yr term from priority
G11C 16/3427G11C 16/0483H10B 41/30H10B 43/30H10B 41/35
40
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.

Claims

exact text as granted — not AI-modified
1 . A method in a NAND-type non-volatile memory string, comprising:
 Serially connecting a plurality of dual-gate devices, wherein each dual-gate device having a first gate dielectric layer provided between a first gate electrode and a lightly doped channel region and a second gate dielectric layer provided between the lightly doped channel region and a second gate electrode and wherein the first gate dielectric layer is charge-storing; and   providing the second gate electrodes as a continuous layer conducting material.   
   
   
       2 . A method as in  claim 1 , further comprising providing the first gate dielectric layer as stacked layers of materials. 
   
   
       3 . A method as in  claim 2  wherein the materials comprise a selected charge-storing material between silicon oxide layers. 
   
   
       4 . A method as in  claim 3  wherein the charge-storing material comprises one or more of: silicon nitride, silicon oxynitride, a graded layer of silicon nitride with spatial variations in oxygen content, nanocrystals of silicon, germanium, tungsten or another metal, aluminum oxide, or a High-K material. 
   
   
       5 . A method as in  claim 1 , wherein the first gate electrode comprises doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more these conductors.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.