Method, system and program product supporting user tracing in a simulator

Abstract

According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.

1 . A method of preparing a simulation model of an electronic design within a data processing system, said method comprising:
 receiving one or more hardware description language (HDL) files declaring a plurality of design entities forming the electronic design, wherein the plurality of design entities includes a plurality of signals and functional logic that define functional operation of the electronic design, wherein said one or more HDL files further include one or more statements specifying an instrumentation entity that monitors at least one design entity among the one or more design entities but does not contribute to functional operation of the electronic design, said one or more statements including a trace array declaration conforming to predetermined syntax, said trace array declaration containing at least:
 a keyword declaring existence of a trace array within the instrumentation entity; and 
 an indication of a monitored signal set including at least one signal among the plurality of signals; and 
   in response to receipt of the one or more HDL files, parsing and processing said one or more HDL files to generate a simulation model formed of representations of instances of the plurality of the design entities and a trace array within at least one of the instances of the plurality of design entities, wherein the trace array is configured to concurrently store multiple values for the monitored signal set obtained over multiple cycles of functional operation of the simulation model; and   placing the simulation model in data storage.   
   
   
       2 . A data processing system for preparing a simulation model of an electronic design, said data processing system comprising:
 means for receiving one or more hardware description language HDL files declaring a plurality of design entities forming the digital design, wherein the plurality of design entities includes a plurality of signals and functional logic that define functional operation of the electronic design, wherein said one or more HDL files further include one or more statements specifying an instrumentation entity that monitors at least one design entity among the one or more design entities but does not contribute to functional operation of the electronic design, said one or more statements including a trace array declaration conforming to predetermined syntax, said trace array declaration containing at least:
 a keyword declaring existence of a trace array within the instrumentation entity; and 
 an indication of a monitored signal set including at least one signal among the plurality of signals; and 
   means, responsive to receipt of the one or more HDL files, for parsing and processing said one or more HDL files to generate a simulation model formed of representations of instances of the plurality of the design entities and a trace array within at least one of the instances of the plurality of design entities, wherein the trace array concurrently stores multiple values for the monitored signal set obtained over multiple cycles of functional operation of the simulation model; and   means for storing the simulation model in data storage.   
   
   
       3 . An apparatus for preparing a simulation model of an electronic design, said apparatus comprising:
 a tangible computer usable medium containing program code, said program code including:
 instructions for receiving one or more hardware description language (HDL) files declaring a plurality of design entities forming the electronic design, wherein the plurality of design entities includes a plurality of signals and functional logic that define functional operation of the electronic design, wherein said one or more HDL files further include one or more statements specifying an instrumentation entity that monitors at least one design entity among the one or more design entities but does not contribute to functional operation of the electronic design, said one or more statements including a trace array declaration conforming to predetermined syntax, said trace array declaration containing at least:
 a keyword declaring existence of a trace array within the instrumentation entity; and 
 an indication of a monitored signal set including at least one signal among the plurality of signals; and 
 
 instructions, responsive to receipt of the one or more HDL files, for parsing and processing said one or more HDL files to generate a simulation model formed of representations of instances of the plurality of the design entities and a trace array within at least one of the instances of the plurality of design entities, wherein the trace array concurrently stores multiple values for the monitored signal set obtained over multiple cycles of functional operation of the simulation model; and 
 instructions for storing the simulation model in data storage. 
   
   
   
       4 . The method of  claim 1 , wherein said receiving further comprises receiving in said trace array declaration an identification of a control signal among said plurality of signals, wherein values assumed by said monitored signal set are stored within the trace array only on those cycles of functional operation during which the control signal is asserted and are not stored on those cycles of functional operation during which the control signal is not asserted. 
   
   
       5 . The method of  claim 1 , wherein parsing and processing said one or more HDL files further comprises parsing and processing the trace array declaration to create within the simulation model an association between a value of the at least one signal comprising said monitored signal set and an enumerated value containing a textual string. 
   
   
       6 . The method of  claim 1 , wherein said trace array declaration includes a keyword specifying a particular type for the trace array among a plurality of different types of trace arrays. 
   
   
       7 . The method of  claim 1 , wherein said receiving comprises receiving the trace array declaration within an HDL file declaring at least one of said plurality of design entities. 
   
   
       8 . The method of  claim 1 , wherein said parsing and processing includes automatically replicating said trace array within a plurality of instances of a design entity declared by an HDL file containing the trace array declaration. 
   
   
       9 . The method of  claim 1 , wherein said receiving comprises receiving said trace array declaration in a comment in the one or more HDL files. 
   
   
       10 . The data processing system of  claim 2 , wherein said means for receiving further comprises means for receiving in said trace array declaration an identification of a control signal among said plurality of signals, wherein values assumed by said monitored signal set are stored within the trace array only on those cycles of functional operation during which the control signal is asserted and are not stored on those cycles of functional operation during which the control signal is not asserted. 
   
   
       11 . The data processing system of  claim 2 , wherein said means for parsing and processing said one or more HDL files further comprises means for parsing and processing the trace array declaration to create within the simulation model an association between a value of the at least one signal comprising said monitored signal set and an enumerated value containing a textual string. 
   
   
       12 . The data processing system of  claim 2 , wherein said trace array declaration includes a keyword specifying a particular type for the trace array among a plurality of different types of trace arrays. 
   
   
       13 . The data processing system of  claim 2 , wherein said means for receiving comprises means for receiving the trace array declaration within an HDL file declaring at least one of said plurality of design entities. 
   
   
       14 . The data processing system of  claim 2 , wherein said means for parsing and processing includes means for automatically replicating said trace array within a plurality of instances of a design entity declared by an HDL file containing the trace array declaration. 
   
   
       15 . The data processing system of  claim 2 , wherein said means for receiving comprises means for receiving said trace array declaration in a comment in the one or more HDL files. 
   
   
       16 . The apparatus of  claim 3 , wherein said instructions for receiving further comprises instructions for receiving in said trace array declaration an identification of a control signal among said plurality of signals, wherein values assumed by said monitored signal set are stored within the trace array only on those cycles of functional operation during which the control signal is asserted and are not stored on those cycles of functional operation during which the control signal is not asserted. 
   
   
       17 . The apparatus of  claim 3 , wherein said instructions for parsing and processing said one or more HDL files further comprises instructions for parsing and processing the trace array declaration to create within the simulation model an association between a value of the at least one signal comprising said monitored signal set and an enumerated value containing a textual string. 
   
   
       18 . The apparatus of  claim 3 , wherein said trace array declaration includes a keyword specifying a particular type for the trace array among a plurality of different types of trace arrays. 
   
   
       19 . The apparatus of  claim 3 , wherein said instructions for receiving comprises instructions for receiving the trace array declaration within an HDL file declaring at least one of said plurality of design entities. 
   
   
       20 . The apparatus of  claim 3 , wherein said instructions for parsing and processing includes instructions for automatically replicating said trace array within a plurality of instances of a design entity declared by an HDL file containing the trace array declaration. 
   
   
       21 . The apparatus of  claim 3 , wherein said instructions for receiving comprise instructions for receiving said trace array declaration in a comment statement in the one or more HDL files.