Design structure for an address translation device

Abstract

An design structure to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The design structure includes an apparatus, which includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, address conflicts between commonly addressed slave devices can be avoided while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

1 . A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
 an apparatus to facilitate communication over an Inter-integrated Circuit (I2C) bus between a host device and a slave device, the slave device sharing a common physical address with at least one other slave device on the I2C bus, the apparatus comprising:
 a detection module to detect an incoming address on an I2C bus; 
 a translation module to translate the incoming address to an outgoing address; and 
 a communication module to communicate data between a host device and a slave device in response to the outgoing address matching a physical address of the slave device. 
   
   
   
       2 . The design structure of  claim 1 , further comprising a correspondence module to uniquely correspond a translation device address to the physical address of the slave device. 
   
   
       3 . The design structure of  claim 2 , wherein the translation device address comprises more than one I2C address. 
   
   
       4 . The design structure of  claim 2 , wherein the correspondence module further comprises means for selectively dynamically modifying the translation device address. 
   
   
       5 . The design structure of  claim 4 , wherein the means for selectively modifying the translation device address comprises at least one of external pins and microcode. 
   
   
       6 . The design structure of  claim 1 , wherein the incoming address comprises a plurality of binary bits, and wherein the translation module serially translates each of the plurality of binary bits. 
   
   
       7 . The design structure of  claim 6 , wherein the translation module flips the each binary bit in response to a mismatch between the each binary bit and a binary bit corresponding to a translation device address. 
   
   
       8 . The design structure of  claim 1 , wherein the communication module comprises a CMOS switch to selectively communicate data between the host device and the slave device. 
   
   
       9 . The design structure of  claim 1 , wherein the design structure comprises a netlist, which describes the apparatus. 
   
   
       10 . The design structure of  claim 1 , wherein the design structure resides on the machine readable storage medium as a data format used for the exchange of layout data of integrated circuits. 
   
   
       11 . A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
 a system to facilitate communication over an I2C bus between a host device and a slave device, the slave device sharing a common physical address with at least one other slave device on the I2C bus, the system comprising:
 a host device; 
 a slave device in communication with the host device over an I2C bus, the slave device sharing a common physical address with at least one other slave device on the I2C bus; and 
   a translation device intermediate the host device and the slave device and connected to the I2C bus, the translation device comprising:   a detection module to detect an incoming address on the I2C bus;   a translation module to translate the incoming address to an outgoing address; and   a communication module to communicate data between the host device and the slave device in response to the outgoing address matching a physical address of the slave device.   
   
   
       12 . The design structure of  claim 11 , wherein the host device is selected from the group consisting of a microcontroller, a microprocessor, and a management module. 
   
   
       13 . The design structure of  claim 11 , wherein the slave device is selected from the group consisting of a RAM, an EEPROM and an I/O device. 
   
   
       14 . The design structure of  claim 11 , wherein the translation device further comprises a correspondence module to uniquely correspond a translation device address to the physical address. 
   
   
       15 . The design structure of  claim 14 , wherein the translation device address comprises more than one I2C address. 
   
   
       16 . The design structure of  claim 14 , wherein the correspondence module further comprises means for selectively dynamically modifying the translation device address. 
   
   
       17 . The design structure of  claim 11 , wherein the incoming address comprises a plurality of binary bits, and wherein the translation module serially translates each of the plurality of binary bits. 
   
   
       18 . The design structure of  claim 17 , wherein the translation module flips the each binary bit in response to a mismatch between the each binary bit and a binary bit corresponding to the translation device address. 
   
   
       19 . The design structure of  claim 11 , wherein the design structure comprises a netlist, which describes the system. 
   
   
       20 . The design structure of  claim 11 , wherein the design structure resides on the machine readable storage medium as a data format used for the exchange of layout data of integrated circuits.