Information processing device and processor

Abstract

A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

1 . A semiconductor device comprising:
 a first slave device;   a first master device outputting a first request control signal from the first master device to the first slave device and a first access address signal assigned to the first slave device when the first master device accesses to the first slave device;   a second master device outputting a second request control signal from the second master device to the first slave device and a second access address signal assigned to the first slave device when the second master device accesses to the first slave device;   a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and   a range setting register holding an address range of which an access of the first master device is permitted,   wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the range setting register comprises a first register to hold an upper limit address, and a second register holding a lower limit address assigned to the first slave device, and   wherein the system bus includes a comparator to compare whether the address outputted by the first master device is within the range shown in the first register and the second register.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the system bus comprises a selector for switching the connection states of the first slave device, the first master device and the second master device, and a selector control circuit for controlling the selector.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the system bus comprises a first illegal address access blocking circuit to detect and block illegal access by the first master device during accessing of the first slave device.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the first illegal address access blocking circuit further detects and blocks illegal access by the second master device during accessing of the first slave device by the second master device.   
     
     
         6 . The semiconductor device according to  claim 1 , comprising:
 a second slave device connected to the system bus,   wherein the system bus comprises a second illegal address access blocking circuit to detect and block illegal access by the first master device during accessing of the second slave device.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein an information held in the range setting register is rewritable by the first master device.