Multi-wafer 3d cam cell

Abstract

A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

1 . A multi-wafer CAM cell comprising:
 at least one compare element located in a first structure which is vertically stacked on top of, or below, at least one storage element located in a second structure, said at least one compare element and said at least one storage element present in separate wafers and are interconnected by at least one vertically conductive filled via hole.   
   
   
       2 . The multi-wafer CAM cell of  claim 1  wherein said at least one compare element is located above said at least one storage element. 
   
   
       3 . The multi-wafer CAM cell of  claim 1  wherein said at least one compare element comprises a plurality of first transistors that have a 9T configuration and said at least one storage element comprises a plurality of second transistors having a 6T configuration. 
   
   
       4 . The multi-wafer CAM cell of  claim 3  wherein said plurality of first transistors are located upon and within a top, active semiconductor layer of a first semiconductor-on-insulator substrate, and said plurality of said second transistors are located upon and within a top, active semiconductor layer of a second semiconductor-on-insulator substrate. 
   
   
       5 . The multi-wafer CAM cell of  claim 4  wherein said first and second semiconductor-on-insulator substrates each include a buried insulating layer directly beneath the top, active semiconductor layer. 
   
   
       6 . The multi-wafer CAM cell of  claim 1  wherein said at least one vertically conductive filled via hole is located within at least one dielectric material. 
   
   
       7 . The multi-wafer CAM cell of  claim 1  wherein said first structure further includes a dielectric material that has conductive filled openings that are in contact with surfaces of at least one first transistor and said second structure further includes a dielectric material that has conductive filled openings that are in contact with surfaces of at least one second transistor. 
   
   
       8 . A multi-wafer CAM cell comprising
 at least one compare element including a plurality of first transistors arranged in a 9T configuration located in a first structure which is vertically stacked on top of at least one storage element including a plurality of second transistors arranged in a 6T configuration located in a second structure, said at least one compare element and said at least one storage element are present in separate wafers and are interconnected by at least one vertically conductive filled via hole.   
   
   
       9 . The multi-wafer CAM cell of  claim 8  wherein said plurality of first transistors are located upon and within a top, active semiconductor layer of a first semiconductor-on-insulator substrate, and said plurality of said second transistors are located upon and within a top, active semiconductor layer of a second semiconductor-on-insulator substrate. 
   
   
       10 . The multi-wafer CAM cell of  claim 9  wherein said first and second semiconductor-on-insulator substrates each include a buried insulating layer directly beneath the top, active semiconductor layer. 
   
   
       11 . The multi-wafer CAM cell of  claim 8  wherein said at least one vertically conductive filled via hole is located within a least one dielectric material. 
   
   
       12 . The multi-wafer CAM cell of  claim 8  wherein said first structure further includes a dielectric material that has conductive filled openings that are in contact with surfaces of at least one of said first transistors and said second structure further includes a dielectric material that has conductive filled openings that are in contact with surfaces of at least one of second transistors. 
   
   
       13 . A method of forming a multi-wafer CAM cell comprising:
 providing a first structure including a plurality of first transistors located upon and within a surface of a first active semiconductor layer;   providing a second structure including a plurality of second transistors located upon and within a surface of a second active semiconductor layer;   bonding a surface of said second structure to a surface of said first structure to provide a bonded structure in which the plurality of first transistors are located above the plurality of second transistors; and   forming at least one vertically conductive filled via to connect said plurality of first transistors to said plurality of second transistors.   
   
   
       14 . The method of  claim 13  wherein said first and second structures each include a dielectric material having conductive filled openings that contact surfaces of said plurality of first and second transistors. 
   
   
       15 . The method  13  wherein said providing first structure includes the steps of attaching a handling substrate to a surface of a dielectric material that encapsulates said plurality of first transistors. 
   
   
       16 . The method of  claim 13  wherein bonding comprises bringing said first and second structures into intimate contact with each other and bonding at a temperature that is about 20° C. or greater. 
   
   
       17 . The method of  claim 13  wherein said at least one vertically filled conductive via is formed by first forming a via by lithography and etching and then filling the via with a conductive material. 
   
   
       18 . The method of  claim 13  wherein said plurality of first transistors have a 9T configuration and said plurality of second transistors have a 6T configuration. 
   
   
       19 . The method of  claim 18  wherein said plurality of first transistors having said 9T configuration are located above said plurality of second transistors having said 6T configuration. 
   
   
       20 . The method of  claim 13  wherein said at least one vertically conductive filled via is aligned to conductive filled openings located within a dielectric material of both said first and second structures.