Dmos device with sealed channel processing

Abstract

A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

1 . An electronic device comprising:
 a substrate, a first portion of the substrate having a first dopant region and a second portion of the substrate having a second dopant region;   an area proximate to both the first and second dopant regions forming a channel, a topmost portion of the channel being coincident with an uppermost surface of the substrate, the surface of the substrate being substantially planar and continuous in an area proximate to the channel; and   at least one transistor, the at least one transistor constructed substantially on the surface of the substrate and having a gate area, a drain area, and a source area, the drain area including the first dopant region and the source area including the second dopant region, the gate area including a gate oxide located over the channel area, the gate oxide being characterized as substantially planar and continuous.   
   
   
       2 . The electronic device of  claim 1  wherein the substrate is silicon. 
   
   
       3 . The electronic device of  claim 1  wherein the substrate is silicon-on-insulator. 
   
   
       4 . The electronic device of  claim 1  wherein the device further comprises a shallow trench isolation feature, the shallow trench isolation feature being comprised of a trench-fill dielectric, the trench-fill dielectric having an uppermost rounded corner in electrical communication with a gate polysilicon located over the gate oxide. 
   
   
       5 . A plurality of transistors, comprising:
 a substrate having a first dopant region having a first dopant type, a first dopant concentration, and a first vertical extent and a second dopant region having a second dopant type, a second dopant concentration, and a second vertical extent;   a first plurality of source and drain regions having a second dopant type in the first dopant region;   a second plurality of source and drain regions having a first dopant type in the second dopant region;   at least a first transistor including a first channel region disposed between at least two of the first plurality of source and drain regions;   at least a second transistor including a second channel region disposed between at least two of the second plurality of source and drain regions;   at least a portion of a top surface of the substrate surrounding the at least first and second transistors including an insulator layer; and   an area proximate to both the first and second dopant regions having a top surface coincident to a top surface of the first dopant region and a top surface of the second dopant region.   
   
   
       6 . The plurality of transistors of  claim 5  wherein the second dopant region has a doping type opposite of the first dopant region. 
   
   
       7 . The plurality of transistors of  claim 5  wherein the plurality of source and drain regions having a second dopant type in the first dopant region have a dopant type opposite to that of the first dopant region, a doping concentration greater than the first dopant region, and a vertical extent less than the first dopant region. 
   
   
       8 . The plurality of transistors of  claim 5  wherein the plurality of source and drain regions having a second dopant type in the first dopant region are spaced from an edge of the first dopant region by a selected distance. 
   
   
       9 . An electronic system, comprising:
 at least one of a controller, a logic device, a memory device and a communications device, connected to each other and including a plurality of transistors in a substrate wherein at least one transistor has a channel region with a positive type doping and at least one transistor has a channel with a negative type doping;   at least a portion of a top surface of the substrate surrounding the at least one transistor channel region with a positive type doping and at least one transistor channel region with a negative type doping first including an insulator layer; and   an area between both the at least one transistor channel region with a positive type doping and at least one transistor channel region with a negative type doping having a top surface coincident to both channel regions and to a top surface of the substrate.   
   
   
       10 . The electronic system of  claim 9  wherein the substrate includes a semiconductive material. 
   
   
       11 . The electronic system of  claim 10  wherein the semiconductive substrate comprises silicon. 
   
   
       12 . The electronic system of  claim 10  wherein the semiconductive substrate comprises germanium. 
   
   
       13 . The electronic system of  claim 10  wherein the semiconductive substrate comprises a compound semiconductor. 
   
   
       14 . The electronic system of  claim 10  wherein the substrate comprises silicon-on-insulator. 
   
   
       15 . A transistor, comprising:
 a substrate, having a first portion of the substrate with a first dopant region and a second portion of the substrate with a second dopant region;   a channel disposed proximate the first and second dopant regions having a top surface coincident with a top surface of the substrate; and   the transistor having a top surface substantially coincident to the surface of the substrate, including a gate area disposed substantially above the channel, a drain contact in the first dopant region, and a source contact in the second dopant region; and   the gate area including a gate oxide disposed in contact with substantially the entirety of the channel area.   
   
   
       16 . The transistor of  claim 15  wherein the substrate is silicon. 
   
   
       17 . The transistor of  claim 15  wherein the substrate is silicon-on-insulator. 
   
   
       18 . The transistor of  claim 15  wherein the substrate comprises a compound semiconductor. 
   
   
       19 . An electronic device, comprising:
 a dielectric stack including at least three distinct dielectric layers on a semiconductive substrate wherein each of the distinct dielectric layers has a selected dielectric constant, a selected oxygen diffusivity rate, and a selected thickness;   at least a top one of the distinct dielectric layers patterned over a first portion of the substrate;   a first dopant region in a portion of the first portion of the substrate;   a portion of the top dielectric layer removed substantially over the first dopant region;   a second dopant region in a portion of the second portion of the substrate; and   at least one of the dopant regions diffused to a selected depth without oxidizing the surface of the substrate by selecting the oxygen diffusivity rate of at least one of the distinct dielectric layers.   
   
   
       20 . The electronic device of  claim 19 , wherein the second portion of the substrate is in proximity to the first portion.