Method of fabricating nonvolatile semiconductor memory device

Abstract

In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

1 .- 6 . (canceled) 
   
   
       7 . The method as claimed in  claim 20 , further comprising:
 forming a first thermal oxide layer on the semiconductor substrate before forming the cell doping region; and   at the same time as forming the tunnel doping region, forming a second thermal oxide layer pattern having greater defects than that of the first thermal oxide layer on the tunnel doping region, wherein the forming the tunnel insulating layer and the gate insulating layer are simultaneous.   
   
   
       8 . The method as claimed in  claim 7 , wherein forming the cell doping region comprises:
 forming a first photoresist pattern defining the cell doping region on the first thermal oxide layer; and   injecting ions of a predetermined first conductive material into the semiconductor substrate using the first photoresist pattern as an injection mask.   
   
   
       9 . The method as claimed in  claim 7 , wherein forming the cell doping region comprises injecting arsenic (As) ions at a dose of as much as about 1×10 13 /cm 2  to about 1.5×10 14 /cm 2  at an energy of about 80 to about 100 KeV. 
   
   
       10 . The method as claimed in  claim 7 , wherein forming the cell doping region comprises injecting phosphorous (P) ions at a dose of as much as about 1×10 13 /cm 2  to about 1.5×10 14 /cm 2  at an energy of about 50 to about 100 KeV. 
   
   
       11 . The method as claimed in  claim 7 , wherein forming the tunnel doping region comprises:
 forming a second photoresist pattern defining the tunnel doping region on the first thermal oxide layer; and   injecting ions of the first conductive material into a predetermined portion of the cell doping region using the second photoresist pattern as an injection mask.   
   
   
       12 . The method as claimed in  claim 7 , wherein forming the tunnel doping region comprises injecting arsenic (As) ions at a dose of as much as about 1×10 13 /cm 2  to about 1×10 15 /cm 2  at an energy of about 30 to about 50 KeV. 
   
   
       13 . The method as claimed in  claim 7 , wherein forming the tunnel doping region comprises injecting phosphorous (P) ions at a dose of as much as about 1×10 13 /cm 2  to about 1×10 15 /cm 2  at an energy of about 20 to about 30 KeV. 
   
   
       14 . The method as claimed in  claim 7 , wherein forming the tunnel insulating layer comprises:
 exposing the semiconductor substrate by removing the second thermal oxide pattern formed on the tunnel doping region using a wet etching method;   removing the second photoresist pattern; and   thermally oxidizing the resultant structure.   
   
   
       15 . The method as claimed in  claim 7 , wherein an etch selectivity between the second thermal oxide pattern and the first thermal oxide layer is about 10:1 to about 50:1. 
   
   
       16 . The method as claimed in  claim 7 , wherein removing the second thermal oxide pattern comprises using a diluted HF or NH 4 F, and a buffered oxide etchant that is a mixed solution of HF and deionized water. 
   
   
       17 . The method as claimed in  claim 7 , further comprising determining a doping concentration of the tunnel doping region by a distance between end portions of the tunnel insulating layer and the cell doping region. 
   
   
       18 . The method as claimed in  claim 7 , wherein forming the tunnel insulating layer comprises forming the tunnel insulating layer to have a width between about 0.15 to about 0.3 μm and a thickness between about 70 to about 120 Å. 
   
   
       19 . The method as claimed in  claim 7 , wherein forming the tunnel insulating layer comprises forming a sidewall of the tunnel insulating layer to have a vertical profile. 
   
   
       20 . A method of fabricating a nonvolatile semiconductor memory device, comprising:
 forming a cell doping region of a first conductive type in a semiconductor substrate;   forming a tunnel doping region of the first conductive type, the tunnel doping region being doped in a higher concentration than the cell doping region, in a region of an upper portion of the cell doping region, a width of the tunnel doping region being smaller than a width of the cell doping region;   forming a tunnel insulating layer on the tunnel doping region, a width of the tunnel insulating layer being smaller than the width of the tunnel doping region;   forming a gate insulating layer covering the cell doping region exposed beyond the tunnel doping region and a channel region; and   forming a gate electrode covering the tunnel insulating layer and on the gate insulating layer.   
   
   
       21 . The method as claimed in  claim 20 , further comprising forming a selection transistor in the semiconductor substrate. 
   
   
       22 . The method as claimed in  claim 21 , wherein forming the tunnel doping region includes forming the high concentration doping region at least partially under the selection transistor. 
   
   
       23 . The method as claimed in  claim 20 , wherein the width of the tunnel doping region and the width of the cell doping region are measured in a channel length direction of the channel region. 
   
   
       24 . The method as claimed in  claim 20 , wherein forming the cell doping region includes completely surrounding the tunnel doping region. 
   
   
       25 . The method as claimed in  claim 20 , wherein a sidewall of the tunnel insulating layer has a vertical profile. 
   
   
       26 . The method as claimed in  claim 20 , wherein the cell doping region is doped with at least one of arsenic (As) ion and phosphorous (P) ions.