Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same

Abstract

First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers.

1 . A manufacturing method of a contact structure of a wire comprising steps of:
 forming a wire on a substrate;   forming a inter-layer reaction layer on the wire by executing annealing process; and   forming a conductive layer electrically connected to the wire via the inter-layer reaction layer.   
     
     
         2 . The method of  claim 1 , wherein the wire is made of a conductive material including aluminum-based material. 
     
     
         3 . The method of  claim 1 , further comprising the step of forming an insulating layer having a contact hole between the wire and the conductive layer. 
     
     
         4 . The method of  claim 3 , wherein the annealing process is executed before forming the insulating layer. 
     
     
         5 . The method of  claim 3 , wherein the annealing process is executed after forming the insulating layer. 
     
     
         6 . The method of  claim 1 , wherein the inter-layer reaction layer includes silicon or transition metal. 
     
     
         7 . The method of  claim 3 , wherein the inter-layer reaction layer is inter-metallic compound layer. 
     
     
         8 . The method of  claim 1 , wherein the conductive layer is made of a transparent conductive material of indium zinc oxide. 
     
     
         9 . The method of  claim 1 , wherein the annealing process is executed in the range of 200-400° C.