Switch memory architectures

Abstract

The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE), (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present invention allows for efficient, potentially unbounded data transfer between two adjacent processes by passing a memory handle and the status registers (memory control information) of the MB. This function may be performed by the ISWITCH.

1 . A method of reconfiguring an existing connection pattern between a grid of processing elements and a grid of memory banks, comprising:
 providing a set of N memory banks (MB) connected via an interconnection switch to a set of N processing elements (PE) such that PEi is connected to MBi for i=1 to N, wherein N is an arbitrary integer;   executing a transformation a distance δ, wherein δ is a constant integer; and   reconnecting PE i  to MB (i+δ)mod N .   
   
   
       2 . The method of  claim 1 , wherein said step of executing a transformation is conducted at a plurality of consecutive clock cycles. 
   
   
       3 . The method of  claim 1 , wherein said step of executing a transformation is conducted at every clock cycle. 
   
   
       4 . The method of  claim 1 , further comprising the transfer of memory control information (MCI) by each PE from MCI(i) to MCI((i+δ) mod N). 
   
   
       5 . The method of  claim 4 , further comprising transferring an unbounded amount of data stored in MBi to processor PEj by connecting MBi to PEj and passing the MCI related to MBi from PEi to PEj, wherein i and j refer to arbitrary integers and wherein j=(i+δ) mod N. 
   
   
       6 . The method of  claim 1 , wherein said reconfiguration is achieved by reconfiguring said interconnection switch. 
   
   
       7 . A method of reconfiguring an existing connection pattern between a grid of processing elements (PE) and a grid of memory banks (MB) via an interconnection switch comprising a grid of switching elements (SE), comprising updating the state of each SE from that of a neighboring SE. 
   
   
       8 . The method of  claim 7 , wherein reconfiguring said existing connection pattern comprises broadcasting a command to all switching elements in said interconnection switch. 
   
   
       9 . The method of  claim 8 , wherein said command specifies a color c and a displacement δ, wherein c refers to a pair of integers specifying the input and output wires involved, and δ refers to a signed integer. 
   
   
       10 . The method of  claim 9 , wherein, in response to said command, each switching element copies the state bit of its c-color switch into the c-color state bit of its δ-neighbor switching element. 
   
   
       11 . The method of  claim 10 , wherein the state wraps around. 
   
   
       12 . The method of  claim 10 , wherein the state is provided as an external input. 
   
   
       13 . The method of  claim 10 , wherein each PE forwards to a neighboring PE, its memory handle, thus relinquishing said processing element's access to the MB. 
   
   
       14 . The method of  claim 13 , wherein the step of forwarding between PEs is accomplished via local connections in a PE grid.