Nand Flash Memory Array Having Pillar Structure and Fabricating Method of the Same

Abstract

The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs.

1 . A NAND flash memory array having a pillar structure, including:
 one or more insulator strips having a pillar structure on a substrate, wherein each pillar is projected at regular intervals;   one or more semiconductor strips having a pillar structure between the insulator strips, wherein each pillar is running parallel with the pillar structure of the insulator strips;   one or more trenches formed by the one or more insulator strips and the one or more semiconductor strips;   two or more dielectric layers including a charge trap layer formed on both sidewalls and a part of bottom of the each trench;   a sidewall gates formed on the dielectric layers;   a first source/drain region formed on the semiconductor strip being on the bottom of the each trench; and   a second source/drain region formed on the projected pillar of the each semiconductor strip.   
   
   
       2 . The NAND flash memory array of  claim 1 ,
 wherein on the second source/drain region formed on one side of the each semiconductor strip, a bit line contact is formed,   a sidewall gate formed along one sidewall of a pillar of the each semiconductor strip where the bit line contact is formed, is a first select gate and is connected to a first select line,   on the second source/drain region formed on the other side of the each semiconductor strip, a source line contact is formed,   a sidewall gate formed along one sidewall of a pillar of the each semiconductor strip where the source line contact is formed, is a second select gate and is connected to a second select line, and   one or more sidewall gates between the first select gate and the second select gate are one or more control gates and are connected to a each word line.   
   
   
       3 . The NAND flash memory array of  claim 2 ,
 wherein on the both sides of the projected pillar of the semiconductor strip, memory cells, which can be operated by the each control gate, are formed, and the memory cells are connected in series along the bit line.   
   
   
       4 . The NAND flash memory array of  claim 1 ,
 wherein the charge trap layer is a nitride layer.   
   
   
       5 . The NAND flash memory array of  claim 1 ,
 wherein the projected pillars of the each semiconductor strip and the projected pillars of the each insulator strip are square pillars, the thickness of the projected square pillar of the semiconductor strip is 30˜50 nm, and   the dose of impurities doped to the projected square pillar of the semiconductor strip is 1×10 16 ˜3×10 18 /cm 3 .   
   
   
       6 . A method of fabricating a NAND flash memory array having a pillar structure, including:
 injecting initial ions into a prepared semiconductor substrate;   forming silicon fin on the ion-injected substrate in the direction of bit line;   depositing an oxide layer on the substrate in order to isolate between the fins;   removing the oxide layer on the silicon fin through a planarization process;   coating a photoresist on the substrate, where the upper side of the silicon fins is exposed;   patterning the photoresist in the direction of word line;   forming trenches with a specific depth and isolated silicon pillars by etching the silicon and the oxide layer along the patterned photoresist and removing the photoresist;   forming two or more dielectric layers including a charge trap layer through a continuous deposition process on the whole surface of the substrate where the trenches are formed;   forming sidewall gates which are spaced each other on both sides of the trench by depositing conductive materials onto the dielectric layers and etching the conductive materials; and   forming source/drains by injecting ions into the whole surface of the substrate where the sidewall gates are formed.   
   
   
       7 . The method of  claim 6 ,
 wherein forming the silicon fin further comprises:   depositing an oxide layer and a nitride layer onto the ions-injected substrate orderly;   patterning the nitride layer; and   forming silicon fin by etching a silicon along the patterned mask.   
   
   
       8 . The method of  claim 7 ,
 wherein the planarization process is the CMP process.   
   
   
       9 . The method of  claim 8 ,
 wherein the continuous deposition process of forming two or more dielectric layers includes depositing a nitride layer as the charge trap layer.   
   
   
       10 . The method of  claim 6 ,
 wherein etching the silicon fins and the oxide layers for forming trenches is characterized that some parts of the oxide layer are remained at the bottom of the trench and that the oxide layer formed one or more insulator strips having a pillar structure in which pillars are projected in the direction of bit line.   
   
   
       11 . The method of  claim 10 , wherein the conductive materials of forming the sidewall gates are poly-silicon or metals, and etching the conductive materials is anisotropic etching. 
   
   
       12 . The method of  claim 10 , wherein injecting ions of forming the source/drains is performed after removing the dielectric layers at the bottom of the trench and on the fins or before removing the dielectric layers. 
   
   
       13 . The method of  claim 7 , wherein etching the silicon fins and the oxide layers for forming trenches is characterized that some parts of the oxide layer are remained at the bottom of the trench and that the oxide layer formed one or more insulator strips having a pillar structure in which pillars are projected in the direction of bit line. 
   
   
       14 . The method of  claim 13 ,
 wherein the conductive materials of forming the sidewall gates are poly-silicon or metals, and etching the conductive materials is anisotropic etching.   
   
   
       15 . The method of  claim 8 ,
 wherein etching the silicon fins and the oxide layers for forming trenches is characterized that some parts of the oxide layer are remained at the bottom of the trench and that the oxide layer formed one or more insulator strips having a pillar structure in which pillars are projected in the direction of bit line.   
   
   
       16 . The method of  claim 15 ,
 wherein the conductive materials of forming the sidewall gates are poly-silicon or metals, and etching the conductive materials is anisotropic etching.   
   
   
       17 . The method of  claim 9 ,
 wherein etching the silicon fins and the oxide layers for forming trenches is characterized that some parts of the oxide layer are remained at the bottom of the trench and that the oxide layer formed one or more insulator strips having a pillar structure in which pillars are projected in the direction of bit line.   
   
   
       18 . The method of  claim 17 ,
 wherein the conductive materials of forming the sidewall gates are poly-silicon or metals, and etching the conductive materials is anisotropic etching.   
   
   
       19 . The NAND flash memory array of  claim 2 ,
 wherein the projected pillars of the each semiconductor strip and the projected pillars of the each insulator strip are square pillars,   the thickness of the projected square pillar of the semiconductor strip is 30˜50 nm, and   the dose of impurities doped to the projected square pillar of the semiconductor strip is 1×10 16 ˜3×10 18 /cm 3 .   
   
   
       20 . The NAND flash memory array of  claim 3 ,
 wherein the projected pillars of the each semiconductor strip and the projected pillars of the each insulator strip are square pillars,   the thickness of the projected square pillar of the semiconductor strip is 30˜50 nm, and   the dose of impurities doped to the projected square pillar of the semiconductor strip is 1×10 16 ˜3×10 18 /cm 3 .