Transistor device and method for manufacturing the same

Abstract

A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect.

1 - 8 . (canceled) 
   
   
       9 . A transistor device comprising:
 a semiconductor substrate having a recess;   a gate insulation layer covering the bottom and sides of the recess;   a gate conductor filling the recess and projected over the semiconductor substrate;   a spacer over the upper sidewall of the gate;   source and drain regions formed over the semiconductor substrate near the spacer; and   a salicide layer formed over the gate, and the source and drain regions.   
   
   
       10 . A transistor device comprising:
 a recess in a surface of semiconductor substrate;   a gate insulation layer formed over an inner side of the recess;   a gate conductor filling the recess in which the gate insulation layer is formed; and   source and drain regions located over the substrate adjacent the recess.   
   
   
       11 . A transistor device according to  claim 10 , wherein an upper portion of the gate conductor projects above the surface of the semiconductor substrate. 
   
   
       12 . A transistor device according to  claim 11 , wherein a spacer is formed over the side wall of a gate insulation portion that is projected above the surface of semiconductor substrate. 
   
   
       13 . A transistor device according to  claim 10 , wherein a salicide layer is formed over a upper portion of the gate and over the source and drain regions. 
   
   
       14 . A transistor device according to  claim 10 , wherein the gate region is made of polysilicon. 
   
   
       15 . A method according to  claim 10 , wherein the gate insulation layer includes one selected from the group consisting of nitride-based oxide, hafnium-based oxide, tantalum-based oxide, and titanium-based oxide. 
   
   
       16 . An apparatus comprising:
 a semiconductor substrate having a recess formed therein;   a gate formed in and protruding from the recess;   insulating layer patterns formed over sidewalls of the gate such that an uppermost surface of the gate projects above the uppermost surface of the insulating layer patterns;   spacers formed over the sidewalls of the gate such that an uppermost surface of the spacers projects above the uppermost surface of the gate; and   a salicide layer formed on the uppermost surface and also the uppermost sidewalls of the gate.   
   
   
       17 . The apparatus of  claim 16 , wherein the insulating layer patterns are composed of an oxide material. 
   
   
       18 . The apparatus of  claim 17 , wherein the oxide material comprises silicon oxide. 
   
   
       19 . The apparatus of  claim 16 , wherein the recess has a depth of approximately 500 Å to 2000 Å. 
   
   
       20 . The apparatus of  claim 16 , wherein the gate is composed of polysilicon. 
   
   
       21 . The apparatus of  claim 16 , further comprising a gate insulation layer formed in the recess and under the gate. 
   
   
       22 . The apparatus of  claim 21 , wherein the gate insulation layer is recessed from the uppermost surface of the gate to expose the upper sidewalls of the gate. 
   
   
       23 . The apparatus of  claim 21 , wherein the gate insulation layer is composed of one selected from the group consisting of nitride-based oxide, hafnium-based oxide, tantalum-based oxide, and titanium-based oxide. 
   
   
       24 . The apparatus of  claim 16 , further comprising lightly doped drain and source and drain regions formed in the semiconductor substrate adjacent to the recess. 
   
   
       25 . The apparatus of  claim 24 , further comprising second salicide layers formed on the lightly doped drain and source and drain regions. 
   
   
       26 . The apparatus of  claim 25 , wherein the second salicide layers are composed of one of cobalt, nickel and titanium. 
   
   
       27 . The apparatus of  claim 16 , wherein a portion of the salicide layers are formed on the gate insulating layer. 
   
   
       28 . The apparatus of  claim 16 , wherein the salicide layers are composed of one of cobalt, nickel and titanium.