Electronic device and method for fabricating the same

Abstract

An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.

1 - 5 . (canceled) 
   
   
       6 . A method for fabricating an electronic device comprising an element formed in a chip region of a substrate, a multilayer structure composed of a plurality of interlayer insulating films formed on the substrate, a wire formed in at least one of the plurality of interlayer insulating films in the chip region, a plug formed in at least one of the plurality of interlayer insulating films in the chip region and providing a connection between the element and the wire or between the individual wires, a seal ring formed in a portion of the multilayer structure composed of the plurality of interlayer insulating films which is located in a peripheral portion of the chip region to extend through the multilayer structure and continuously surround the chip region, and a stress absorbing wall formed in a portion of the multilayer structure composed of the plurality of interlayer insulating film which is located outside the seal ring to extend through the multilayer structure and discretely surround the seal ring, the method comprising the steps of:
 forming, in one plurality of interlayer insulating films, a first depressed portion to be filled with the plug or the wire, a second depressed portion to be filled with a part of the seal ring, and a third depressed portion to be filled with a part of the stress absorbing wall;   filling a conductive film in each of the first, second, and third depressed portions to form the plug or the wire, the part of the seal ring, and the part of the stress absorbing wall; and   forming a protective film on the multilayer structure composed of the plurality of interlayer insulating films provided with the wire, the plug, the seal ring, and the stress absorbing wall.   
   
   
       7 . The method of  claim 6 , wherein the seal ring has a seal ring structure in the which the seal ring surrounds the chip region in a double or higher-order multiple structure, and
 the seal ring structure has a first seal ring and a second seal ring which is provided outside the first seal ring so as to surround the first seal ring.   
   
   
       8 . The method of  claim 7 , wherein
 a passivation film is formed on the multilayer structure composed of the plurality of interlayer insulating films, and   the passivation film has an opening on only one of the first seal ring or on the second seal ring and not the other.   
   
   
       9 . The method of  claim 6 , wherein the stress absorbing walls in a double or higher-order multiple structure are surrounding the seal ring. 
   
   
       10 . The method of  claim 9 , wherein gap portions between respective discrete portions of each of the stress absorbing walls in the double or higher-order multiple structure are not aligned in rows. 
   
   
       11 . The method of  claim 9 , wherein each of the components of the one of the stress absorbing walls in the double or higher-order multiple structure which is formed at a position most distant from the seal ring has a shorter length along a direction in which the seal ring extends than each of the components of the other stress absorbing wall or walls. 
   
   
       12 . The method of  claim 6 , wherein in each of the seal ring and the stress absorbing wall is composed of at least one of W, Al, and Cu.