Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program

Abstract

A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a second acquiring device to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device, a determining device to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, and a management device to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data.

1 . (canceled) 
   
   
       2 : A computer readable medium storing a program for controlling a bus access device which is connected to a main memory via a bus, reading out data from the main memory via the bus, and transferring the readout data to a data cache, the program comprising:
 means for instructing a computer to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquire access hint information is acquired from a processor;   means for instructing the computer to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device;   means for instructing the computer to monitor a data transfer instruction to the bus access device and identify data access of the data if an address of the data transfer instruction is equal to the start address of the access hint information;   means for instructing the computer to determine a preload unit count on the basis of the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including one of:   the data access interval divided by a clock speed of the processor;   a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access;   a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and   means for instructing the computer to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the data cache ahead of the data access of the data.   
   
   
       3 : The computer readable medium according to  claim 2 , further comprising:
 means for instructing the computer to store address translation information in an address translation information cache; and   means for instructing the computer to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the address translation information cache ahead of address translation using the address translation information.   
   
   
       4 : A computer readable medium storing a program for controlling an address translation device which is connected to a main memory via a bus, reading out address translation information from the main memory via the bus, and transferring the readout address translation information to an address translation information cache, the program comprising:
 means for instructing a computer to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquire access hint information is acquired from a processor;   means for instructing the computer to acquire system information which represents a transfer delay time in transfer of address translation information via the bus by the address translation device;   means for instructing the computer to monitor an address translation instruction to the address translation device and identify address translation using the address translation information if an address of the address translation instruction is equal to the start address of the access hint information;   means for instructing the computer to determine a preload unit count on the basis of the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including one of:   the data access interval divided by a clock speed of the processor;   a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access;   a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and   means for instructing the computer to instruct the address translation device to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the address translation information cache ahead of the address translation using the address translation information.   
   
   
       5 : The computer readable medium according to  claim 4 , further comprising:
 means for instructing the computer to store data in a data cache; and   means for instructing the computer to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the data cache ahead of a data access of the data.   
   
   
       6 : A computer system comprising:
 a main memory;   a data cache;   a bus;   a bus access device that reads out data from the main memory via the bus and transfers the readout data to the data cache;   a preload controller that controls the bus access device, including:   a first acquiring device configured to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquire access hint information is acquired from a processor;   a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device;   an identifying device configured to monitor a data transfer instruction to the bus access device and identify data access of the data if an address of the data transfer instruction is equal to the start address of the access hint information;   a determining device configured to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including one of:   the data access interval divided by a clock speed of the processor;   a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access;   a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and   a first management device configured to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the data cache ahead of the data access of the data.   
   
   
       7 : The computer system according to  claim 6 , further comprising:
 an address translation information cache configured to store address translation information;   an address translation unit configured to translate an address of the data on the basis of the address translation information; and   a second management device configured to instruct the bus access device or the address translation unit to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the address translation information cache ahead of address translation using the address translation information.   
   
   
       8 : A computer system comprising:
 a main memory;   an address translation information cache;   a bus;   an address translation device that reads out address translation information from the main memory via the bus and transfers the readout address translation information to the address translation information cache;   a preload controller that controls the address translation device, including:   a first acquiring device configured to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquire access hint information is acquired from a processor;   a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of address translation information via the bus by the address translation device;   an identifying device configured to monitor an address translation instruction to the address translation device and identify address translation using the address translation information if an address of the address translation instruction is equal to the start address of the access hint information;   a determining device configured to determine a preload unit count on the basis of the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including one of:   the data access interval divided by a clock speed of the processor;   a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access;   a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and   a first management device configured to instruct the address translation device to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the address translation information cache ahead of the address translation using the address translation information.   
   
   
       9 : The computer system according to  claim 8 , further comprising:
 a data cache configured to store data;   a bus access device configured to read out the data from the main memory via the bus, and transfer the readout data to the data cache; and   a second management device configured to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the data cache ahead of a data access of the data.   
   
   
       10 : A bus system comprising:
 a bus access device that reads out data from a main memory via a bus and transfers the readout data to a data cache; and   a preload controller that controls the bus access device, including:   a first acquiring device configured to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquire access hint information is acquired from a processor;   a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device;   an identifying device configured to monitor a data transfer instruction to the bus access device and identify data access of the data if an address of the data transfer instruction is equal to the start address of the access hint information;   a determining device configured to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including one of:   the data access interval divided by a clock speed of the processor;   a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access;   a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and   a first management device configured to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the data cache ahead of the data access of the data.   
   
   
       11 : The bus system according to  claim 10 , further comprising:
 an address translation information cache configured to store address translation information;   an address translation unit configured to translate an address of the data on the basis of the address translation information; and   a second management device configured to instruct the bus access device or the address translation unit to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the address translation information cache ahead of address translation using the address translation information.   
   
   
       12 : A bus system comprising:
 an address translation device that reads out address translation information from a main memory via a bus and transfers the readout address translation information to an address translation information cache;   a preload controller that controls the address translation device, including:   a first acquiring device configured to acquire access hint information which represents a start address and a data access interval to the main memory, wherein the acquire access hint information is acquired from a processor;   a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of address translation information via the bus by the address translation device;   an identifying device configured to monitor an address translation instruction to the address translation device and identify address translation using the address translation information if an address of the address translation instruction is equal to the start address of the access hint information;   a determining device configured to determine a preload unit count on the basis of the data access interval represented by the access hint information and the transfer delay time represented by the system information, the preload unit count being the transfer delay time divided by a data access time, the data access time including one of:   the data access interval divided by a clock speed of the processor;   a first estimated time based on a behavior of the processor obtained from a command sequence to be executed during the data access;   a second estimated time calculated by multiplying a number of commands included in the command sequence and an average processing time; and   a first management device configured to instruct the address translation device to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the address translation information cache ahead of the address translation using the address translation information.   
   
   
       13 : The bus system according to  claim 12 , further comprising:
 a data cache configured to store data;   a bus access device configured to read out the data from the main memory via the bus, and transfer the readout data to the data cache; and   a second management device configured to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the data cache ahead of a data access of the data.