US2008308895A1PendingUtilityA1

Semiconductor device

Assignee: KIM CHANG NAMPriority: Dec 31, 2004Filed: Aug 15, 2008Published: Dec 18, 2008
Est. expiryDec 31, 2024(expired)· nominal 20-yr term from priority
Inventors:Chang Nam Kim
H10W 10/0145H10W 10/17H10P 14/60H10P 10/00H10D 84/0151H10D 84/0144H10D 84/038
50
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Claims

Abstract

A semiconductor device and fabricating method thereof are provided. A dual gate oxide layer is formed by thermal oxidation after carrying out a prescribed pre-processing on an STI edge, which results in a high quality oxide layer by thermal oxidation and a uniformly maintained gate oxide layer thickness of a high voltage device area. The present invention includes a semiconductor substrate divided into an active area and an inactive area, the active area including a high voltage device area and a low voltage device area; a device isolation layer on the inactive area of the semiconductor substrate; and a gate oxide layer on the high voltage device area of the semiconductor substrate, the gate oxide layer having a uniform thickness.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a semiconductor substrate having an active area and an inactive area, the active area including a high voltage device area and a low voltage device area;   a device isolation layer on the inactive area of the semiconductor substrate; and   a gate oxide layer on the high voltage device area of the semiconductor substrate, the gate oxide layer having an uniform thickness.   
   
   
       2 . The semiconductor device of  claim 1 , further comprising a buffer oxide layer on an edge of the device isolation layer. 
   
   
       3 . The semiconductor device of  claim 1 , the device isolation layer comprising:
 a sacrifice oxide layer on a portion adjacent to the semiconductor substrate;   a liner oxide layer on the sacrifice layer; and   a gap-fill oxide layer on the liner oxide layer.   
   
   
       4 . The semiconductor device of  claim 1 , the device isolation layer comprising:
 a liner oxide layer on a portion adjacent to the semiconductor substrate having a round cross-section at a portion contacting with a top surface of the semiconductor substrate; and   a gap-fill oxide layer on the liner oxide layer.   
   
   
       5 . The semiconductor device of  claim 1 , wherein the device isolation layer includes a portion projected from a top surface of the semiconductor substrate and wherein a lateral side of the projected portion has an exterior angle greater than 90° relative to the top surface of the semiconductor substrate. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the gate oxide layer comprises a thermal oxide layer formed through an thermal oxidation process. 
   
   
       7 - 17 . (canceled)

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