Microcomputer and dividing circuit

Abstract

Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

1 .- 21 . (canceled) 
     
     
         22 . A microcomputer formed on a single semiconductor device comprising:
 a CPU having a 32-bit general purpose register; and   a memory coupled to said CPU,   wherein said CPU is capable of processing at least one conditional branch instruction and at least one unconditional branch instruction,   wherein the memory stores instructions to be processed by said CPU,   wherein each of the instruction bit lengths of the conditional branch instruction and the unconditional branch instruction is 16 bits, and   wherein a displacement length of the conditional branch instruction is smaller than the displacement length of the unconditional branch instruction.   
     
     
         23 . The microcomputer according to  claim 22 , wherein the displacement length of the conditional branch instruction is 8 bits. 
     
     
         24 . The microcomputer according to  claim 22 , wherein the displacement length of the unconditional branch instruction is 12 bits. 
     
     
         25 . The microcomputer according to  claim 22 , wherein the memory is a cache memory. 
     
     
         26 . A microcomputer formed on a single semiconductor device comprising:
 a RISC type CPU having a 32-bit general purpose register; and   a memory coupled to said RISC type CPU,   wherein said RISC type CPU is capable of processing at least one conditional branch instruction and at least one unconditional branch instruction,   wherein the memory stores instructions to be processed by said RISC type CPU,   wherein each of the instruction bit lengths of the conditional branch instruction and the unconditional branch instruction is 16 bits, and   wherein a displacement length of the conditional branch instruction is smaller than the displacement length of the unconditional branch instruction.   
     
     
         27 . The microcomputer according to  claim 26 , wherein the displacement length of the conditional branch instruction is 8 bits. 
     
     
         28 . The microcomputer according to  claim 26 , wherein the displacement length of the unconditional branch instruction is 12 bits. 
     
     
         29 . The microcomputer according to  claim 26 , wherein the memory is a cache memory. 
     
     
         30 . A microcomputer formed on a single semiconductor device comprising:
 a CPU having a 32-bit general purpose register;   a RAM coupled to said CPU;   a DMA controller coupled to said RAM; and   a memory coupled to said CPU,   wherein said CPU is capable of processing at least one conditional branch instruction and at least one unconditional branch instruction,   wherein the memory stores instructions to be processed by said CPU, and   wherein a displacement length of the conditional branch instruction is smaller than the displacement length of the unconditional branch instruction.   
     
     
         31 . The microcomputer according to  claim 30 , wherein the memory is a cache memory. 
     
     
         32 . The microcomputer according to  claim 30 , wherein each of the instruction bit lengths of the conditional branch instruction and the unconditional branch instruction is 16 bits. 
     
     
         33 . The microcomputer according to  claim 32 , wherein the displacement length of the conditional branch instruction is 8 bits. 
     
     
         34 . The microcomputer according to  claim 32 , wherein the displacement length of the unconditional branch instruction is 12 bits. 
     
     
         35 . A microcomputer formed on a single semiconductor device comprising:
 a CPU having general purpose registers and a program counter; and   a memory coupled to said CPU,   wherein said CPU is capable of processing at least one data transfer instruction, at least one conditional branch instruction and at least one unconditional branch instruction,   wherein each of the instruction bit lengths of the data transfer instruction, the conditional branch instruction and the unconditional branch instruction is 16 bits,   wherein the memory stores instructions to be processed by said CPU,   wherein the conditional branch instruction includes a first area for a first displacement,   wherein the unconditional branch instruction includes a second area for a second displacement,   wherein a length of the first displacement of the conditional branch instruction is smaller than a length of the second displacement of the unconditional branch instruction,   wherein the data transfer instruction includes a third area for a third displacement and a fourth area for destination register information for designating the general purpose register where the data is loaded,   wherein the branch address of the conditional branch instruction is obtained based on the first displacement in the first area of the conditional branch instruction and an address in the program counter,   wherein the branch address of the unconditional branch instruction is obtained based on the second displacement in the second area of the unconditional branch instruction and an address in the program counter, and   wherein 32 bits source data of the data transfer instruction is obtained from a memory location indicated by an address obtained based on the third displacement in the third area of the data transfer instruction and an address in the program counter, and the source data is loaded into one of the general purpose registers which is designated by the fourth area of the data transfer instruction.   
     
     
         36 . The microcomputer according to  claim 35 , wherein the displacement length of the data transfer instruction is 8 bits. 
     
     
         37 . The microcomputer according to  claim 35 , wherein the program counter is 32 bit length. 
     
     
         38 . The microcomputer according to  claim 35 , wherein the general purpose register is 32 bit length. 
     
     
         39 . The microcomputer according to  claim 35 , wherein the displacement length of the conditional branch instruction is 8 bits. 
     
     
         40 . The microcomputer according to  claim 35 , wherein the displacement length of the unconditional branch instruction is 12 bits. 
     
     
         41 . The microcomputer according to  claim 35 , wherein the memory is a cache memory. 
     
     
         42 . The microcomputer according to  claim 35 , wherein the address of the memory location is obtained by adding the displacement in the first area with an address in the program counter. 
     
     
         43 . The microcomputer according to  claim 35 ,
 wherein the data transfer instruction further includes a fifth area having an operation code defining a data transfer operation,   wherein the operation code includes data size information of the data to be transferred, and   wherein the displacement is shifted by 2 bits and the shifted displacement is added to the address in the program counter when the data size information indicates that the data size is 32 bits.