Semiconductor Devices and Methods for Fabricating the Same

Abstract

Semiconductor devices and methods of fabricating the same are disclosed. An illustrated semiconductor device fabricating method includes forming a titanium and titanium-nitride (Ti/TiN) metal layer on a lower oxide layer; forming an aluminum metal layer on the Ti/TiN metal layer; forming an indium tin oxide (ITO) layer on the aluminum metal layer; and patterning the ITO layer, the aluminum metal layer, and the Ti/TiN metal layer by photolithography to form a metal layer pattern and to expose a surface of the lower oxide layer, thereby facilitating a process of filling inter-wiring spaces occurring between adjacent lines of a metal layer pattern by producing a metal layer pattern having a reduced aspect ratio.

1 . A semiconductor device, comprising:
 a semiconductor substrate including a lower oxide layer;   a titanium and titanium-nitride (Ti/TiN) metal layer pattern on the semiconductor substrate including the lower oxide layer;   an aluminum metal layer pattern on the Ti/TiN metal layer pattern;   an indium tin oxide layer pattern on the aluminum metal layer pattern; and   a dielectric layer covering the Ti/TiN metal layer pattern, the aluminum metal layer pattern, and the indium tin oxide layer pattern, wherein the Ti/TiN metal layer pattern, the aluminum metal layer pattern, and the indium tin oxide layer pattern have coinciding patterns leaving an inter-wiring space between said metal layer patterns, so that a surface of the lower oxide layer between said metal layer patterns is exposed, and wherein the dielectric layer covers the exposed surface of the lower oxide layer.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the dielectric layer is between lines of metal layer pattern in the inter-wiring space above the exposed surface of the lower oxide layer. 
   
   
       3 . The semiconductor device of  claim 2 , wherein the dielectric layer completely fills the inter-wiring space. 
   
   
       4 . The semiconductor device of  claim 3 , wherein the dielectric layer leaves no void in the inter-wiring space. 
   
   
       5 . The semiconductor device of  claim 3 , wherein the metal layer pattern has an aspect ratio determined by a height of the metal layer pattern divided by a width of the inter-wiring space. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the Ti/TiN metal layer has a thickness of 1,000˜20,000 Å. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the aluminum metal layer has a thickness of 1,000˜20,000 Å. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the ITO layer has a composition of In x Sn y O z . 
   
   
       9 . The semiconductor device of  claim 8 , wherein x=0.2˜0.3. 
   
   
       10 . The semiconductor device of  claim 9 , wherein y=0.2˜0.3. 
   
   
       11 . The semiconductor device of  claim 10 , wherein z=0.4˜0.6. 
   
   
       12 . The semiconductor device of  claim 1 , wherein the ITO layer has a refractive index (n) of 1.0˜2.0. 
   
   
       13 . The semiconductor device of  claim 12 , wherein the ITO layer has an absorption coefficient (k) of 0.1˜0. 
   
   
       14 . The semiconductor device of  claim 1 , wherein the ITO layer has an absorption coefficient (k) of 0.1˜0.