Computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLS) supported on a multi-core CPU chip, and employing a software-implemented multi-mode parallel graphics rendering subsystem

Abstract

A computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem. The computing system includes (i) CPU memory space for storing one or more graphics-based applications, (ii) a multi-core GPU chip including one or more CPU-cores, a memory controller for controlling the CPU memory space, and an interconnect network, and (iii) one or more external graphics cards supporting multiple GPUs and being connected to the multi-core CPU chip by way of a data communication interface. The computing system also includes (i) one or more graphics cards supporting multiple GPUs and being connected to the multi-core CPU chip by way of a data communication interface, (ii) the multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation, (iii) a plurality of graphic processing pipelines (GPPLs) implemented using some of the CPU-cores, and (iv) an automatic mode control module. During the run-time of the graphics-based application, the automatic mode control module automatically controls the mode of parallel operation of the MMPGRS, so that the GPUs are driven in a parallelized manner.

1 . A computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLs) supported on a multi-core CPU chip, said computing system comprising:
 CPU memory space for storing one or more graphics-based applications and a graphics library for generating graphics commands and data (GCAD) during the execution of the graphics-based application;   a multi-core CPU chip having
 multiple CPU-cores; 
 a memory controller for controlling access to said CPU memory space, and 
 an interconnect network; 
   a bridge circuit operably connecting said memory space and said multi-core CPU chip; and   one or more external graphics cards supporting multiple GPUs and being connected to said CPU/GPU fusion-architecture chip by way of a data communication interface;   a multi-mode parallel graphics rendering system (MMPGRS) supporting multiple modes of parallel operation selected from the group consisting of object division, image division, and time division, and wherein each mode of parallel operation includes at least three stages, namely, decomposition, distribution and recomposition;   a plurality of graphic processing pipelines (GPPLs), implemented using some of said CPU-cores, and supporting a parallel graphics rendering process that employs one of said object division, image division and/or time division modes of parallel operation in order to execute graphic commands, process graphics data, and render pixel-composited images containing graphics for display on a display device during the run-time of said graphics-based application, and said display device being connectable to an external graphics cards; and   an automatic mode control module for automatically controlling the mode of parallel operation of said multi-mode parallel graphics rendering subsystem during the run-time of said graphics-based application, so that said GPUs are driven in a parallelized manner under the control of said automatic mode control module, during the run-time of said graphics-based application; and   wherein said multi-mode parallel graphics rendering subsystem further includes:
 (i) a decomposition module for supporting the decomposition stage of parallel operation; 
 (ii) a distribution module for supporting the distribution stage of parallel operation; and 
 (iii) a recomposition module for supporting the recomposition stage of parallel operation; and 
   wherein said automatic mode control module, said decomposition module, said distribution module and said recomposition module are each implemented as a software package.   
     
     
         2 . The computing system of  claim 1 , wherein during operation,
 (i) said decomposition module divides the stream of graphic commands and data according to the required parallelization mode, operative at any instant in time;   (ii) said distribution module uses said bridge circuit to distribute graphic commands and data to said multiple GPUs on board the external graphics cards,   (iii) said recomposition module uses said bridge circuit to transfer composited pixel data between said recomposition module and said multiple GPUs during the recomposition stage, and   (iv) finally recomposited pixel data sets are displayed as graphical images on said display device.   
     
     
         3 . The computing system of  claim 1 , wherein said automatic mode control module employs profiling of scenes in said graphics-based application. 
     
     
         4 . The computing system of  claim 3 , wherein said profiling of scenes in said graphics-based application, is carried out in real-time during run-time of said graphics-based application. 
     
     
         5 . The computing system of  claim 4 , wherein said real-time profiling of scenes in said graphics-based application involves (i) collecting and analyzing performance data associated with said MMPGRS and said computing system, during application run-time, (ii) constructing scene profiles for the image frames associated with particular scenes in said particular graphics-based application, and (iii) maintaining said scene profiles in a application/scene profile database that is accessible to said automatic mode control module during run-time, so that during the run-time of said graphics-based application, said automatic mode control module can access and use said scene profiles maintained in said application/scene profile database and determine how to dynamically control the modes of parallel operation of said multi-mode parallel graphics rendering subsystem to optimize system performance. 
     
     
         6 . The computing system of  claim 3 , wherein said automatic mode control module employs real-time detection of scene profile indices programmed within pre-profiled scenes of said graphics-based application;
 wherein said pre-profiled scenes are analyzed prior to run-time, and indexed with said scene profile indices; and   wherein and mode control parameters (MCPs) corresponding to said scene profile indices, are stored within a application/scene profile database accessible to said automatic mode control module during application run-time.   
     
     
         7 . The computing system of  claim 6 , wherein during run-time, said automatic mode control module automatically detects said scene profile indices and uses said detected said scene profile indices to access corresponding MCPs from said application/scene profile database so as to determine how to dynamically control the modes of parallel operation of said MMPGRS to optimize system performance. 
     
     
         8 . The computing system of  claim 3 , wherein said automatic mode control module employs real-time detection of mode control commands (MCCs) programmed within pre-profiled scenes of said graphics-based application;
 wherein said pre-profiled scenes are analyzed prior to run-time, and said MCCs are directly programmed within the individual image frames of each scene; and   wherein during run-time, said automatic mode control module automatically detects said MCCs along the graphics command and data stream, and uses said MCCs so as to determine how to dynamically control the modes of parallel operation of said MMPGRS to optimize system performance.   
     
     
         9 . The computing system of  claim 3 , wherein said automatic mode control module employs a user interaction detection (UID) mechanism for real-time detection of the user's interaction with said computing system. 
     
     
         10 . The computing system of  claim 9 , wherein, in conjunction with said scene profiling, said automatic mode control module also uses said UID mechanism to determine how to dynamically control the modes of parallel operation of the MMPGRS to optimize system performance, at any instance in time during the run-time of said graphics-based application. 
     
     
         11 . The computing system of  claim 1 , which further comprises a bridge circuit disposed between said CPU memory space and said one or more CPUs. 
     
     
         12 . The computing system of  claim 11 , wherein said bridge circuit is a North memory bridge circuit disposed between said CPU memory space and said one or more CPUs. 
     
     
         13 . The computing system of  claim 11 , wherein said bridge circuit is a South bridge circuit disposed between said CPU memory space and said one or more CPUs. 
     
     
         14 . The computing system of  claim 1 , wherein said multi-core CPU chip implements multiple GPPLs, and said external graphics card supports at least one GPU, and wherein said GPPLs and said GPU are driven in a parallelized manner during the run-time of said graphics-based application. 
     
     
         15 . The computing system of  claim 1 , wherein said display device is a device selected from the group consisting of an flat-type display panel, a projection-type display panel, and other image display devices. 
     
     
         16 . The computing system of  claim 1 , wherein said computing system is a machine selected from the group consisting of a PC-level computer, information server, laptop, game console system, portable computing system, and any computational-based machine supporting the real-time generation and display of 3D graphics. 
     
     
         17 . The computing system of  claim 2 , wherein said recomposition module is implemented across two or more of said GPUs. 
     
     
         18 . The computing system of  claim 1 , wherein said each said software package is implemented in said memory space. 
     
     
         19 . The computing system of  claim 2 , wherein only one of said GPUs is designated as the primary GPU and is responsible for driving said display unit with a final pixel image composited within a frame buffer (FB) maintained by said primary GPU, and all other GPUs function as secondary GPUs, supporting the pixel image recompositing process.