Memory device capable of communicating with host at different speeds, and data communication system using the memory device

Abstract

Provided is a memory device for high speed communication including a low speed data communication port and a low speed data input/output circuit, and a data communication system using the memory device. The memory device includes a high speed port interface for transmitting or receiving data to or from a host at a high speed, and a low speed port interface for transmitting or receiving data to or from the host at a low speed.

1 . A memory device comprising:
 a high speed port interface exchanging data with a host at a high speed;   a high speed data communication block exchanging high speed data with the host through the high speed port interface;   a low speed port interface exchanging low speed data with the host at a low speed;   a low speed data communication block maintaining operating setting conditions of the memory device and exchanging low speed data with the host through the low speed port interface; and   control logic controlling the operations of the high speed data communication block and the low speed data communication block, wherein the control logic enables the high speed communication block to exchange the high speed data with the host through the high speed port interface and enables the low speed communication block to exchange the operating setting conditions of the memory device through the low speed interface.