Multiple layer printed circuit board having misregistration testing pattern

Abstract

A method of testing for misregistration in a multiple layer printed circuit board includes providing an electrical test pattern on one or more layers of the board, testing for an electrical signal between the test pattern and a test reference, and determining layer-to-layer misregistration based on the results of the testing. A method of manufacturing a multiple layer board that is configured to facilitate non-destructive testing of layer-to-layer misregistration includes forming an electrical test pattern on a first layer and forming a corresponding electrical test reference on a second layer. Then, a connecting pathway is formed between the test reference and the test pattern, including the first and second layers, with testing for an electrical signal between the test reference and the test pattern determining layer-to-layer misregistration of the first layer with respect to the second layer.

1 . A method of manufacturing a multiple layer printed circuit board configured to facilitate testing of layer-to-layer misregistration, the method comprising the steps of:
 forming a plurality of electrical test traces extending from near a through-hole site on a first layer, a first end of each of the plurality of electrical test traces located adjacent the through-hole site and a second end of each of the plurality of electrical test traces located away from the through-hole site, wherein at least two of the plurality of electrical test traces are electrically isolated from each other;   forming an electrically conductive connecting pathway between the first layer and a second layer at the through-hole site;   testing for an electrical continuity between the electrically conductive connecting pathway and each of the plurality of electrical test traces; and   determining layer-to-layer misregistration of the first layer with respect to the second layer based on the electrical continuity.   
   
   
       2 . A multiple layer printed circuit board configured to facilitate non-destructive testing of layer-to-layer misregistration within the board, the multiple layer board comprising:
 an electrical test pattern on a first layer of the multiple layer board, the electrical test pattern comprising a plurality of electrical traces extending from near a through-hole site, wherein at least two of the plurality of electrical traces are electrically isolated from each other;   a corresponding electrical test reference on a second layer of the multiple layer board;   a first connecting pathway between the electrical test reference and the electrical test pattern; and   a second connecting pathway between the first layer and the second layer at the through-hole site,   wherein a test for misregistration between the first and second layers includes a test for an electrical continuity between the second connecting pathway and the electrical test reference or for an electrical discontinuity across at least part of the electrical test pattern.   
   
   
       3 . The multiple layer board of  claim 2 , wherein the plurality of electrical traces each further comprise a first end located adjacent the through-hole site and a second end located away from the through hole site, the second end including a trace pad. 
   
   
       4 . The multiple layer board of  claim 3 , wherein the test reference comprises a plurality of probe pads located to correspond to the plurality of trace pads. 
   
   
       5 . The multiple layer board of  claim 4 , wherein the trace pads and the probe pads are laid out in an orderly pattern to facilitate testing of the electrical continuity. 
   
   
       6 . The multiple layer board of  claim 2 , wherein the test reference comprises a plurality of probe pads located to correspond to the plurality of electrical traces. 
   
   
       7 . The multiple layer board of  claim 2 , wherein the electrical test pattern is normally conductive and misregistration between the first and second layers results in disruption of the conductivity. 
   
   
       8 . The multiple layer board of  claim 7 , wherein the second connecting pathway comprises a non-plated through-hole. 
   
   
       9 . The multiple layer board of  claim 2 , wherein the electrical test reference is normally not conductive with respect to the second connecting pathway, wherein the second connecting pathway is electrically conductive, and wherein misregistration between the first and second layers results in conductivity between the electrical test reference and the second connecting pathway. 
   
   
       10 . The multiple layer board of  claim 9 , wherein the second connecting pathway comprises a plated through-hole. 
   
   
       11 . The multiple layer board of  claim 2 , further comprising a plurality of electrical test patterns each formed on a different layer of the multiple layer board and wherein the second connecting pathway connects the different layers of the multiple layer board. 
   
   
       12 . The multiple layer board of  claim 11 , wherein the electrical test reference is located on an outer layer of the multiple layer board and each of the plurality of electrical test patterns is located on inner layers of the multiple layer board. 
   
   
       13 . The multiple layer board of  claim 2 , further comprising a plurality of test references and a plurality of corresponding test patterns spaced about the board. 
   
   
       14 . The multiple layer board of  claim 2 , wherein the multiple layer board comprises four test references and four corresponding sets of test patterns spaced generally near four corners of the multiple layer board, each of the sets of test patterns including one or more test patterns formed on a different layer of the multiple layer board. 
   
   
       15 . A multiple layer printed circuit board configured to facilitate testing of layer-to-layer misregistration, comprising:
 a plurality of electrical test traces extending from near a through-hole site on a first layer, a first end of each of the plurality of electrical test traces located adjacent the through-hole site and a second end of each of the plurality of electrical test traces located away from the through-hole site, wherein at least two of the plurality of electrical test traces are electrically isolated from each other;   an electrically conductive connecting pathway formed between the first layer and a second layer at the through-hole site;   wherein a test for misregistration between the first and second layers includes a test for an electrical continuity between the electrically conductive connecting pathway and each of the plurality of electrical test traces.   
   
   
       16 . The multiple layer printed circuit board of  claim 15 , wherein the second end of each of the plurality of electrical test traces comprises a trace pad. 
   
   
       17 . The multiple layer board of  claim 16 , further comprising a test reference formed on the second layer, the test reference comprising a plurality of probe pads located to correspond to the plurality of trace pads. 
   
   
       18 . The multiple layer board of  claim 17 , wherein the trace pads and the probe pads are laid out in an orderly pattern to facilitate testing of the electrical continuity. 
   
   
       19 . The multiple layer board of  claim 15 , further comprising a test reference formed on the second layer, the test reference comprising a plurality of probe pads located to correspond to the plurality of electrical test traces.