Nonvolatile semiconductor memory device and method of manufacturing the same

Abstract

A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.

1 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer;   a plurality of memory cells provided on the semiconductor layer, the memory cells comprising:   a first dielectric film provided by covering the surface of the semiconductor layer;   a plurality of charge storage layers, each of which is provided above the insulating material and on the first dielectric film;   a plurality of second dielectric films, each of which is provided on the each charge storage layer;   a plurality of conductive layers, each of which is provided on the each second dielectric film; and   an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.   
   
   
       2 . The device according to  claim 1 , further comprising:
 an isolation region is formed inside the semiconductor layer and the semiconductor substrate with the bottom end thereof extending deeper than the bottom end of the insulating material.   
   
   
       3 . The device according to  claim 1 , wherein
 the each impurity diffusion layer of the each memory cell is integrated.   
   
   
       4 . The device according to  claim 1 , wherein
 the insulating material is provided at a plurality of locations along the surface of the semiconductor substrate.   
   
   
       5 . The device according to  claim 1 , wherein
 the insulating material is provided at a plurality of locations along the surface of the semiconductor substrate, and the impurity diffusion layer is formed inside the semiconductor layer and the semiconductor substrate with a portion of a lower part of the impurity diffusion layer extending deeper than an upper surface of the insulating materials.   
   
   
       6 . The device according to  claim 1 , wherein
 the each impurity diffusion layer of the each memory cell is integrated, and the integrated impurity diffusion layer has areas where impurity concentrations are higher and those where impurity concentrations are lower.   
   
   
       7 . The device according to  claim 1 , further comprising:
 a semiconductor compound layer containing at least one of nitrogen and carbon and provided at an interface at least between the upper surface of the insulating material and the semiconductor layer of the interfaces between the semiconductor layer and the semiconductor substrate, and the insulating material.   
   
   
       8 . The device according to  claim 1 , further comprising:
 a semiconductor compound layer containing at least one of nitrogen and carbon and provided by covering the entire surface of the insulating material.   
   
   
       9 . The device according to  claim 1 , further comprising:
 a semiconductor compound layer containing at least nitrogen, having nitrogen concentrations higher than those of the insulating material, and provided at an interface at least between the upper surface of the insulating material and the semiconductor layer of the interfaces between the semiconductor layer and the semiconductor substrate, and the insulating material.   
   
   
       10 . The device according to  claim 1 , further comprising:
 at least one select-gate transistor comprising:   the first dielectric film;   a layer made of a material identical to that of the each charge storage layer, at least a portion thereof being partially provided on the first dielectric film at a position deviating from above the insulating material;   a layer made of a material identical to that of the each second dielectric film and provided on the layer made of the material identical to that of the each charge storage layer;   a layer made of a material identical to that of the each conductive layer, provided on the layer made of the material identical to that of the each second dielectric film, and connected to the layer made of the material identical to that of the each charge storage layer by cutting through the layer made of the material identical to that of the each second dielectric film; and   an impurity diffusion layer for the select-gate transistor, at least a portion thereof being formed inside the semiconductor layer at an area deviating from above the insulating material and at least a portion of the bottom end thereof being provided by the upper surface of the insulating material.   
   
   
       11 . The device according to  claim 1 , wherein
 the semiconductor layer has the upper surface in the area above the insulating material higher than that in the area deviating from above the insulating material, and a step in a boundary part between the area above the insulating material and the area deviating from above the insulating material.   
   
   
       12 . The device according to  claim 1 , wherein
 the first dielectric film has an equal thickness in an area above the insulating material and in an area deviating from above the insulating material, the upper surface in the area above the insulating material higher than that in the area deviating from above the insulating material, and a step in a boundary part between the area above the insulating material and the area deviating from above the insulating material.   
   
   
       13 . The device according to  claim 1 , further comprising:
 at least one select-gate transistor comprising:   the first dielectric film;   a layer made of a material identical to that of the each charge storage layer, at least a portion thereof being partially provided on the first dielectric film at an area deviating from above the insulating material;   a layer made of a material identical to that of the each second dielectric film and provided on the layer made of the material identical to that of the each charge storage layer;   a layer made of a material identical to that of the each conductive layer, provided on the layer made of the material identical to that of the each second dielectric film, and connected to the layer made of the material identical to that of the each charge storage layer by cutting through the layer made of the material identical to that of the each second dielectric film; and   an impurity diffusion layer for the select-gate transistor, at least a portion thereof being formed inside the semiconductor layer at an area deviating from above the insulating material and at least a portion of the bottom end thereof being provided by the upper surface of the insulating material,   wherein the select-gate transistor is provided by extending over a step part formed in a boundary part between an area above the insulating material and an area deviating from above the insulating material, a portion thereof in the area above the insulating material is formed higher than that in the area deviating from above the insulating material, and a bottom thereof is formed in a stepped shape.   
   
   
       14 . The device according to  claim 1 , wherein
 the first dielectric film is formed thinner in an area deviating from above the insulating material than in an area above the insulating material.   
   
   
       15 . The device according to  claim 1 , further comprising:
 at least one select-gate transistor comprising:   the first dielectric film formed thinner in an area deviating from above the insulating material than in an area above the insulating material;   a layer made of a material identical to that of the each charge storage layer, provided partially on the first dielectric film in an area deviating from above the insulating material, and formed thicker than the each charge storage layer of the each memory cell provided in the area above the insulating material;   a layer made of a material identical to that of the each second dielectric film and provided on the layer made of the material identical to that of the each charge storage layer;   a layer made of a material identical to that of the each conductive layer, provided on the layer made of the material identical to that of the each second dielectric film, and connected to the layer made of the material identical to that of the each charge storage layer by cutting through the layer made of the material identical to that of the each second dielectric film; and   an impurity diffusion layer for the select-gate transistor, at least a portion thereof being formed inside the semiconductor layer at an area deviating from above the insulating material and at least a portion of the bottom end thereof being provided by the upper surface of the insulating material.   
   
   
       16 . The device according to  claim 15 , wherein
 the layer made of the material identical to that of the each charge storage layer complements a difference in film thickness between the area deviating from above the insulating material and the area above the insulating material of the first dielectric film to form the upper surface thereof as high as that of the each charge storage layer of the each memory cell provided in the area above the insulating material.   
   
   
       17 . The device according to  claim 1 , wherein
 the semiconductor substrate is a silicon substrate,   the semiconductor layer is a silicon crystal layer,   the first dielectric film is a silicon oxide film,   the each charge storage layer is a polysilicon layer,   the each second dielectric film is a metal oxide film, and   the each conductive layer is a metal compound layer containing silicon.   
   
   
       18 . The device according to  claim 1 , wherein
 the semiconductor substrate is a silicon substrate,   the semiconductor layer is a silicon crystal layer,   the first dielectric film is a silicon oxide film,   the each charge storage layer is a compound film containing silicon and nitrogen,   the each second dielectric film is an oxide film, and   the each conductive layer is a layer comprising of a metal element or silicon element.   
   
   
       19 . A method of manufacturing a nonvolatile semiconductor memory device, comprising:
 providing a sacrificial layer inside at least one recess formed in a surface layer part by being partially lowered from a surface of a semiconductor substrate and providing a semiconductor layer by covering the surface of the sacrificial layer and that of the semiconductor substrate;   providing a first dielectric film and a charge storage layer in a stacked structure by covering the surface of the semiconductor layer and forming a plurality of trenches extending into the semiconductor substrate positioned lower than the sacrificial layer by cutting through the charge storage layer, the first dielectric film, the semiconductor layer, and the sacrificial layer;   forming cavities communicatively connected to the each trench inside the semiconductor substrate by selectively removing the sacrificial layer from inside the semiconductor substrate and providing an insulating material inside the each trench until an upper surface of the insulating material becomes higher than that of the first dielectric film while the insulating material being provided inside the cavities via the each trench;   providing a second dielectric film and a conductive layer in the stacked structure by covering the surface of the insulating material provided inside the each trench and that of the charge storage layer and leaving a plurality of stacked structures comprised of the conductive layer, the second dielectric film, and the charge storage layer at least above the insulating material and on the first dielectric film by partially removing the conductive layer, the second dielectric film, and the charge storage layer provided at least inside the cavities above the insulating material until the surface of the first dielectric film is exposed; and   forming an impurity diffusion layer by partially feeding impurities at least into the semiconductor layer above the insulating material using the each stacked structure as a mask or feeding fully the impurities into at least the semiconductor layer in advance before removing the sacrificial layer.   
   
   
       20 . The method according to  claim 19 , wherein
 before removing the sacrificial layer, the charge storage layer is made harder to etch than the sacrificial layer in advance or the charge storage layer is formed of a material that is harder to etch than that of the sacrificial layer.