Thermally enhanced semiconductor devices

Abstract

One embodiment relates to a circuit. In this circuit, a first semiconductor device with a first geometry is associated with a first region of a semiconductor body within a first isolation structure. A second semiconductor device with a geometry that matches the first geometry is associated with a second region of the semiconductor body within a second isolation structure. A member, which spans the semiconductor body between the first region and the second region, thermally couples the first region to the second region while retaining electrical isolation therebetween. Other circuits and methods are also disclosed.

1 . A circuit, comprising:
 a first semiconductor device having a first geometry and being associated with a first region within a first isolation structure;   a second semiconductor device having a geometry that matches the first geometry and being associated with a second region within a second isolation structure; and   a member, which spans the semiconductor body between the first region and the second region, that is configured to thermally couple the first region to the second region while retaining electrical isolation therebetween.   
   
   
       2 . The circuit of  claim 1 , where the member thermally couples the first region to the second region so the regions are separated by a thermal resistance of no more than approximately 100 K-m/W. 
   
   
       3 . The circuit of  claim 2 , where the member electrically isolates the first region from the second region by an effective electrical reactance at frequencies near a bandwidth of the circuit of at least approximately 10 kΩ. 
   
   
       4 . The circuit of  claim 1 , where the first region comprises:
 a first electrical resistance region having a first electrical resistance; and   a second electrical resistance region with a second electrical resistance that is greater than the first electrical resistance.   
   
   
       5 . The circuit of  claim 4 , where the first electrical resistance region has a first doping concentration and the second electrical resistance region has a second doping concentration that is lower than the first doping concentration. 
   
   
       6 . The circuit of  claim 4 , further comprising:
 a contact that couples the member to the second electrical resistance region.   
   
   
       7 . The circuit of  claim 1 , where the member comprises inter-digitated fingers. 
   
   
       8 . The circuit of  claim 7 , where the inter-digitated fingers comprise a relatively high reactance finger nearer to the first and second semiconductor devices and relatively low reactance finger further from the first and second devices. 
   
   
       9 . The circuit of  claim 7 , where the inter-digitated fingers comprise a poly layer; and further comprising:
 an oxide layer that separates the poly layer from the semiconductor body, where poly layer is configured such that heat is exchanged between the first and second devices by passing though the oxide layer and into the inter-digitated fingers.   
   
   
       10 . The circuit of  claim 7 , where the inter-digitated fingers comprise a metal layer; and further comprising:
 a contact connecting the metal layer to the semiconductor body.   
   
   
       11 . The circuit of  claim 1 , where the first and second semiconductor devices comprise bipolar junction transistors having matched geometries and formed within a single semiconductor body. 
   
   
       12 . A circuit, comprising:
 a first region of a semiconductor body associated with a first isolation structure in which a first device is formed, where the first region comprising a first electrical resistance region and a second electrical resistance region that has a greater resistivity than the first electrical resistance region, the first electrical resistance region being under at least the first device;   a second region of the semiconductor body associated with a second isolation structure in which a second device is formed, where the second region comprises a third electrical resistance region and a fourth electrical resistance region that has a greater resistivity than the third electrical resistance region, the third resistance region being under at least the second device; and   a member that is configured to thermally couple the first region to the second region while retaining electrical isolation therebetween.   
   
   
       13 . The circuit of  claim 12 , where the member overlies the first electrical resistance region and the third electrical resistance region and spans the semiconductor body therebetween. 
   
   
       14 . The circuit of  claim 13 , where the member comprises:
 a metal layer;   a contact coupling the metal layer to a poly layer over the first electrical resistance region; and   another contact coupling the metal layer to the third electrical resistance region.   
   
   
       15 . The circuit of  claim 13 , where the member comprises:
 at least one poly layer that directly overlies an oxide layer associated with the first electrical resistance region and an oxide layer associated with the third electrical resistance region.   
   
   
       16 . The circuit of  claim 12 , where the member overlies the second electrical resistance region and the fourth electrical resistance region and spans the semiconductor body therebetween. 
   
   
       17 . The circuit of  claim 16 , where the member comprises:
 a first metal layer;   a contact coupling the first metal layer to the second electrical resistance region;   a second metal layer;   a contact coupling the second metal layer to the fourth electrical resistance region; and   a dielectric through which heat can flow that separates the first metal layer and the second metal layer.   
   
   
       18 . The circuit of  claim 16 , where the member comprises:
 at least one poly layer that directly overlies oxide layers respectively associated with the second electrical resistance region and the fourth electrical resistance region.   
   
   
       19 . The circuit of  claim 16 , where the member comprises:
 a metal layer;   a contact that couples the metal to the second electrical resistance region; and   another contact that couples the metal to the fourth electrical resistance region.   
   
   
       20 . A method for forming a circuit, comprising:
 forming isolation structures in a semiconductor body; where the isolation structures are adapted to electrically isolate first and second regions within the semiconductor body;   in the first and second regions, forming first and second relatively-high electrical resistance regions, respectively, by performing an implant that forms first and second relatively-low electrical resistance regions, respectively;   in the first and second relatively-low electrical resistance regions, forming first and second devices, respectively; and   forming a member that thermally couples the first and second relatively-high electrical resistance regions to one another and retains electrical isolation therebetween.