Thin film transistor array panel and a manufacturing method thereof

Abstract

A method of manufacturing a thin film transistor array panel and a thin film transistor array panel are provided. The method includes: forming a gate line and a storage electrode line on a substrate; forming a gate insulating layer on the gate line and the storage electrode line; forming a semiconductor layer on the gate insulating layer; forming a data line and a drain electrode on the semiconductor layer; depositing a passivation layer on the data line and the drain electrode; forming a photoresist including a first portion and a second portion on the passivation layer; etching the passivation layer using the photoresist to expose a portion of the data line and a first portion of the gate insulating layer; removing the second portion of the photoresist; etching the passivation layer and the first portion of the gate insulating layer using the photoresist to expose a second portion of the gate insulating layer and a portion of the drain electrode and a portion of the gate line; depositing a conductive film on the first transformed photoresist; and removing the first transformed photoresist to form a pixel electrode connected to the exposed portion of the drain electrode.

1 . A thin film transistor array panel comprising:
 a gate line and a storage electrode line formed on a substrate;   a gate insulating layer formed on the gate line and the storage electrode line;   a semiconductor layer formed on the gate insulating layer;   a data line and a drain electrode formed on the semiconductor layer;   a passivation layer formed on the data line and a first portion of the drain electrode; and   a pixel electrode formed on the gate insulating layer and a second portion of the drain electrode and separated from the passivation layer,   wherein the pixel electrode has a border substantially equal to that of the passivation layer.   
   
   
       2 . The panel of  claim 1 , wherein the passivation layer and the gate insulating layer have contact holes exposing a portion of the gate line and a portion of the data line, and
 wherein the panel further comprises contact assistants formed in the contact holes, wherein the contact assistants have borders substantially equal to those of the contact holes.   
   
   
       3 . The panel of  claim 1 , wherein the second portion of the drain electrode overlaps the storage electrode line. 
   
   
       4 . The panel of  claim 3 , wherein the second portion of the drain electrode has a wider width than that of the remaining drain electrode, and
 a portion of the storage electrode line which is overlapped with the drain electrode has a wider width than that of the remaining storage electrode line.   
   
   
       5 . The panel of  claim 1 , wherein the semiconductor layer has substantially the same planar shape as the data line and the drain electrode. 
   
   
       6 . The panel of  claim 1 , wherein the panel is for a liquid crystal display. 
   
   
       7 . The panel of  claim 1 , wherein the panel is for an organic light emitting display. 
   
   
       8 . The panel of  claim 1 , further comprising:
 a storage capacitor formed between the storage electrode line and the pixel electrode.