Shared pipeline architecture for motion vector prediction and residual decoding

Abstract

A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.

1 . A video decoding system configured with a multi-stage shared pipeline architecture for carrying out the H.264 CABAC and CALVC entropy decoding processes in Main Profile and High Profile, comprising:
 a first stage for grouping macro block properties into 4×4 sub blocks;   a second stage for performing separation of coefficients and run level pairs;   a third stage for performing run level pair decoding;   a fourth stage for performing 4×4 block zigzag transform, DC/AC coefficient merging, and motion vector prediction; and   a fifth stage for performing 8×8 transforms in the High Profile, and is skipped in the Main Profile.   
   
   
       2 . The system of  claim 1  wherein the fourth stage has four split modes for the motion vector prediction: 16×16, 16×8, 8×16, and 8×8, and each split mode has its own motion vector computation logic, reference picture index computation, and frame field scaling. 
   
   
       3 . The system of  claim 1  wherein B-type picture decoding has a dual channel read write structure, and logic index ID searching is performed on a block by block basis. 
   
   
       4 . The system of  claim 3  wherein a block N+1 logic index ID is calculated while motion vector prediction is performed for block N, thereby mitigating searching time. 
   
   
       5 . The system of  claim 1  further comprising a memory interfaced to the first stage via an N-bit bus, wherein there are a plurality of syntax groups of N-bit data inside each macro block, and the memory provides the first stage with the length for every syntax group. 
   
   
       6 . The system of  claim 5  wherein the first stage includes a memory control state machine that collects information about macro block properties and groups it into 4×4 sub blocks for all predictions. 
   
   
       7 . The system of  claim 5  wherein N=24, and the N-bits designate current macro block properties including at least one of: intra prediction, inter prediction, skip mode, raw data mode, macro block ID, slice ID, direct mode, macro block split mode, sub block split mode which can be down to 4×4 for luma and 2×2 for chroma and all corresponding intra prediction flag and motion vector differences on X and Y direction, picture reference index for forward and backward predictions, CABAC bit map and level, and CALVC run level information. 
   
   
       8 . The system of  claim 1  wherein the first stage includes a residual decoder state machine for carrying out residual decoding of I-type, P-type, and B-type pictures. 
   
   
       9 . The system of  claim 1  wherein the first stage includes a PCM raw data state machine for carrying put a PCM raw data mode. 
   
   
       10 . The system of  claim 1  further comprising a dual channel read memory interfaced to the first stage via an N-bit bus, wherein for frame pictures, channel  1  of the memory is for even macro block row reference reads and channel  2  of the memory is for odd macro block reference read, and for field pictures, channel  1  of the memory is for a top field picture and channel  2  of the memory is for a bottom field picture reference read. 
   
   
       11 . The system of  claim 1  further comprising a dual channel read memory interfaced to the first stage via an N-bit bus, wherein if a current decoding picture is a frame picture and a corresponding reference picture is a field picture, either top field or bottom field, then both channel  1  and channel  2  of the memory have the same reference picture, thereby facilitating B-type picture decoding. 
   
   
       12 . The system of  claim 11  wherein if current decoding picture is a B-type picture, then the reference picture is read from a DDR SDRAM for direct mode motion vector prediction. 
   
   
       13 . The system of  claim 1  further comprising a dual channel read memory interfaced to the first stage via a 128-bit bus, and for every macro block there are five data beats of 128 bits that contain macro block properties, logical ID and physical ID of every 8×8 block inside a 16×16 macro block, and motion vectors of every 4×4 block. 
   
   
       14 . The system of  claim 1  further comprising a line buffer used for motion vector prediction of inter prediction and intra prediction mode decoding. 
   
   
       15 . The system of  claim 1  further comprising a dual channel write memory interfaced to the fifth stage via an N-bit bus, wherein if a current decoding picture is a field picture, either top field or bottom field, then the top field is written out through channel  1  and the bottom field is written out through channel  2  of the memory, thereby facilitating B-type picture decoding. 
   
   
       16 . The system of  claim 1  further comprising a dual channel write memory interfaced to the fifth stage via an N-bit bus, wherein if a current decoding picture is a reference picture, then properties for each macro block are saved to a DDR SDRAM and read back when current decoding picture is a B-type picture. 
   
   
       17 - 18 . (canceled) 
   
   
       19 . The system of  claim 1  further comprising:
 a macro block quantized DCT coefficient memory interfaced to the fifth stage via a 128-bit bus, for storing dequantized DC/AC coefficients.   
   
   
       20 . The system of  claim 1  where the second stage includes a state machine for carrying out separation of coefficients and run level pairs. 
   
   
       21 . The system of  claim 1  where the third stage includes a state machine for carrying out run level pair decoding. 
   
   
       22 . The system of  claim 1  where the fourth and fifth stages include a state machine for carrying out transform, DC/AC coefficient merging, and motion vector prediction. 
   
   
       23 . (canceled) 
   
   
       24 . A video decoding system configured with a multistage shared pipeline architecture for carrying out the H.264 CABAC and CALVC entropy decoding processes in Main Profile and High Profile, comprising:
 a first stage including a memory control state machine that collects information about macro block properties and groups it into 4×4 blocks for all predictions;   a second stage for performing separation of coefficients and run level pairs;   a third stage for performing run level pair decoding;   a fourth stage for performing 4×4 block zigzag transform, DC/AC coefficient merging, and motion vector prediction, wherein the fourth stage has four split modes for the motion vector prediction: 16×16, 16×8, 8×16, and 8×8, and each split mode has its own motion vector computation logic, reference picture index computation, and frame field scaling;   a fifth stage for performing 8×8 transforms in the High Profile, and is skipped in the Main Profile; and   dual read channels and dual write channels for direct mode motion vector prediction of B-type pictures.   
   
   
       25 . (canceled)