Thin film transistors and fabrication methods

Abstract

A method of fabricating a low temperature semiconductor thin film device is described. The method includes: forming one or more metal lines on a substrate; forming a conductive contact to a said metal line; forming a thin film device having: a first amorphous silicon region, wherein a portion of the region covers a said conductive contact; and a gate dielectric layer; and a second amorphous silicon layer; forming a silicide of first and second amorphous silicon material with a deposited metallic material; depositing an insulating material; and forming conductive contacts and top metal interconnects to couple said first and second amorphous silicon regions.

1 . A method of fabricating a semiconductor thin film device, the method including:
 depositing a first amorphous silicon layer on a substrate;   patterning and etching the first amorphous silicon layer;   depositing a first dielectric layer;   patterning and etching the first dielectric layer, the etched region including a buried contact region on the first amorphous silicon layer;   depositing a second amorphous silicon layer;   patterning and etching the second amorphous silicon layer;   depositing a second dielectric layer;   etching the second dielectric layer to define dielectric spacer regions adjacent to second amorphous silicon geometry side walls;   depositing a metallic material for the purpose of silicide formation of first and second amorphous silicon material; and   silicide formation of the metallic material, wherein the second amorphous silicon layer is fully silicided in the buried contact region, and wherein the first amorphous silicon layer is partially or fully silicided in the buried contact region.   
   
   
       2 . The method of  claim 1 , including patterning and dopant implantation of one or both of first and second amorphous silicon layers to modify conductivity. 
   
   
       3 . The method of  claim 1 , including laser annealing of one or both of first and second amorphous silicon layers to form single crystal or polycrystalline silicon material. 
   
   
       4 . The method of  claim 1 , wherein the substrate includes one of a semiconductor, polymer, metallic, insulator, glass, and composite material. 
   
   
       5 . The method of  claim 1 , wherein the first dielectric region includes one of an oxide, an oxy-nitride, a nitride and any other insulating material. 
   
   
       6 . The method of  claim 1 , further including patterning and implanting dopant after the patterning and etching of the second amorphous silicon layer and prior to the second dielectric deposition to form doped source and drain regions in the first amorphous silicon layer. 
   
   
       7 . The method of  claim 1 , wherein one or both of the first and second amorphous silicon layer thicknesses is less than or equal to thirty nano-meters. 
   
   
       8 . The method of  claim 3 , wherein the laser anneal maintains a temperature less than or equal to four-hundred centigrade at the surface of the substrate layer. 
   
   
       9 . The method of  claim 6 , wherein the implant dose is greater than or equal to 2.0*10 15  atoms per square centimeter. 
   
   
       10 . A method of fabricating a semiconductor thin film device, including:
 forming one or more metal lines on a substrate;   depositing a first dielectric material to isolate the metal lines;   planarizing the first dielectric surface;   patterning and etching the first dielectric layer to form first contact openings;   depositing one or more barrier materials and tungsten to fill the first contacts;   polishing the tungsten material to form tungsten plugs in the contact regions;   depositing a first amorphous silicon layer;   patterning and etching the first amorphous silicon layer, the remaining silicon regions including a region covering a said first contact opening having tungsten material;   depositing a second dielectric layer;   depositing a second amorphous silicon layer;   patterning and etching the second amorphous silicon layer;   depositing a third dielectric layer;   patterning and etching the third dielectric layer to define second contact regions;   depositing a top metal for the purpose of forming interconnects; and   patterning and etching the top metal, wherein the top metal interconnects couple first and second silicon regions.   
   
   
       11 . The method of  claim 10 , including patterning and dopant implantation of one or both of first and second amorphous silicon layers. 
   
   
       12 . The method of  claim 10 , including laser annealing of one or both of first and second amorphous silicon layers to form single crystal or polycrystalline silicon material. 
   
   
       13 . The method of  claim 10 , wherein the substrate includes one of a semiconductor, polymer, metallic, insulator, glass, and composite material. 
   
   
       14 . The method of  claim 10 , wherein the second dielectric region includes one of an oxide, an oxy-nitride, a nitride and any other insulating material. 
   
   
       15 . The method of  claim 10 , including patterning and etching the second dielectric layer after said second dielectric is deposited and prior to said second amorphous silicon deposition, the etched region further including a buried contact region on the first amorphous silicon layer. 
   
   
       16 . The method of  claim 10 , wherein after the second amorphous silicon layer is deposited and prior to depositing the third dielectric layer further including:
 depositing a spacer dielectric layer;   etching the spacer dielectric layer to define spacer dielectric regions adjacent to second amorphous silicon geometry side walls;   depositing a metallic material for the purpose of silicide formation of first and second amorphous silicon material; and   silicide formation of the metallic material, wherein the second amorphous silicon layer is fully silicided in a said buried contact region, and wherein the first amorphous silicon layer is partially or fully silicided in the buried contact region.   
   
   
       17 . The method of  claim 10 , wherein one or both of the first and second amorphous silicon layer thicknesses is less than or equal to thirty nano-meters. 
   
   
       18 . The method of  claim 12 , wherein the laser anneal maintains a temperature less than or equal to four-hundred centigrade on the said one or more metal lines on the substrate. 
   
   
       19 . A method of fabricating a low temperature semiconductor thin film device, including:
 forming one or more metal lines on a substrate;   forming a conductive contact to a said metal line;   forming a thin film device having:
 a first amorphous silicon region, wherein a portion of the region covers a said conductive contact; and 
 a gate dielectric layer; and 
 a second amorphous silicon layer; 
   forming a silicide of first and second amorphous silicon material with a deposited metallic material;   depositing an insulating material; and   forming conductive contacts and top metal interconnects to couple said first and second amorphous silicon regions.   
   
   
       20 . The method of  claim 19 , wherein the processing temperature is below four-hundred centigrade for forming said thin film device and said silicide.