Method for cache correction using functional tests translated to fuse repair

Abstract

A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

1 . A method of handling a defect in a storage array of a microprocessor, comprising:
 operating the microprocessor in a normal processing mode to carry out a functional test procedure which utilizes the storage array;   collecting fault data in a trace array during the functional test procedure;   identifying a location of the defect in the storage array using the fault data; and   repairing the defect by setting one of a plurality of fuses which reroutes access requests for the location to one of a plurality of redundant elements for the storage array, wherein the functional test procedure is carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets another one or more of the fuses.   
   
   
       2 . The method of  claim 1 , further comprising:
 determining that a repair for the defective location is possible by examining availability of the fuses.   
   
   
       3 . The method of  claim 1  wherein said repairing sets a soft fuse. 
   
   
       4 . The method of  claim 1  wherein the fault data includes an error syndrome and a failing address. 
   
   
       5 . The method of  claim 1  wherein the storage array is a cache memory for a processing unit of the microprocessor, and the functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory. 
   
   
       6 . A processing unit comprising:
 at least one processor core which carries out program instructions;   a cache memory which temporarily stores values used by said at least one processor core, said cache memory including one or more arrays of redundant elements;   control logic which operates said at least one processor core in a normal processing mode to carry out a functional test procedure utilizing said cache memory, collects fault data during the functional test procedure, identifies a location of a defect in said cache memory using the fault data, and repairs the defect by setting one of a plurality of fuses which reroutes access requests for the location to one of said redundant elements;   a built-in self test engine which carries out a nonfunctional test of said cache memory prior to the functional test procedure; and   a scan controller which sets another one or more of said fuses based on results from said built-in self test engine.   
   
   
       7 . The processing unit of  claim 6  wherein said control logic further determines that a repair for the defective location is possible by examining availability of said fuses. 
   
   
       8 . The processing unit of  claim 6  wherein said fuses are soft fuses. 
   
   
       9 . The processing unit of  claim 6  wherein the fault data includes an error syndrome and a failing address. 
   
   
       10 . The processing unit of  claim 6  wherein said control logic includes a trace array to store the fault data during the functional test procedure. 
   
   
       11 . A computer system comprising:
 one or more processors which process program instructions;   a system memory device; and   a cache memory connected to at least one of said one or more processors and to said system memory device for temporarily storing values that are used by said one or more processors, said cache memory including one or more arrays of redundant elements; and   control logic which operates said one or more processors in a normal processing mode to carry out a functional test procedure utilizing said cache memory, collects fault data during the functional test procedure, identifies a location of a defect in said cache memory using the fault data, and repairs the defect by setting one of a plurality of fuses which reroutes access requests for the location to one of said redundant elements;   a built-in self test engine which carries out a nonfunctional test of said cache memory prior to the functional test procedure; and   a scan controller which sets another one or more of said fuses based on results from said built-in self test engine.   
   
   
       12 . The computer system of  claim 11  wherein said control logic includes a trace array to store the fault data during the functional test procedure. 
   
   
       13 . The computer system of  claim 11  wherein said control logic includes:
 a scan controller for setting said fuses; and   an SCOM controller for identifying the location of the defect using the fault data.   
   
   
       14 . The computer system of  claim 11  further comprising an interface port which transmits test software from an external test unit to said control logic. 
   
   
       15 . The computer system of  claim 14  wherein said test software acts as a low-level kernel which creates a random access sequence causing varying loads of traffic in said cache memory using a test pattern based on a random seed.